# How to Calculate your ASIC Unit Cost

Finding your ASIC unit cost is one of the most important steps prior to starting any ASIC design activities. If you are a semiconductor company – your company’s profit is highly dependent on the ASIC production cost. This post helps you understand the different cost components related to ASIC manufacturing.

In today’s competitive market, profits or losses must be estimated from day one. Moreover, if you are shipping products into a competitive market, your ability to reduce cost will determine your success in the short and long run.

The two major components in ASIC costs are:

• ASIC development costs
• ASIC unit cost

The concept described in this guide is applicable both for small ASICs (such as BlueTooth or IoT chips) and for large chips such as Crypto ASICs or networking chips. This paper will focus only on ASIC unit cost

## ASIC Unit Cost Breakdown

ASIC manufacturing costs include wafer cost, assembly cost, and test cost. While there are additional related costs, these three components cover 95% of any ASIC cost.

Yield is also a key component of ASIC cost that is often overlooked in early-stage price calculation. There are three types of yield figures: wafer yield, assembly yield, and test yield. You want, of course, the yield to be as high as possible.

The following table describes the different ASIC cost components:

## Silicon Die Cost

The first component in the finished ASIC production cost is the silicon die cost.

We start with calculating the number of dies per wafer (DPW). AnySilicon provides a simple die per wafer (DPW) calculator that can help with this task.

Input: die size (x,y)

Output: dies per wafer (DPW)

Once the number of dies per wafer is available, it is possible to divide the wafer price with the DPW figure to find the die cost.

If the die size is not available at this stage of the project, you can assume a few sizes to get best-case and worst-case scenarios.

## Wafer Test Cost

Testing each die is time-consuming and therefore introduces a price adder to the total ASIC cost, but in some cases it is necessary. The price of wafer testing is correlated to the number of seconds the test is performed.

Wafer testing is based on renting test machines. This means that as a customer, you are paying for renting the Automated Test Equipment (ATE) and the wafer prober to test your silicon.

If the tester’s hourly rate is (for example) \$100 and the test duration is 1 second,  your wafer test cost will be: \$0.0278 per chip.

The wafer yield figure will be available when the wafer sort is completed.

## Packaging Cost

Whether your chip is assembled in a QFN or a WLCSP package type, you need first to collect all the costs associated with the assembly process. This may include:

• Wafer back-grinding (thinning)
• Dicing of wafer (singulation)
• Substrate material (in case of BGA package)
• Assembly/package cost

Here too, like in wafer testing, you end up with an assembly yield figure that impacts the ASIC production cost. The typical figure for assembly yield is 97%-99%.

## Final Test Cost

All ASICs need to go through a quality test before they are shipped to the customer. Therefore, every ASIC supply chain ends with a Final Test. It’s an automated electronic test that screens the good and the bad chips.

Like with wafer testing, your cost is based on renting the test equipment from the vendor and paying per hour while the vendor operates the test for you.

If the tester’s hourly rate is, for example, \$100 and the test duration is 1 second. Your final test cost will be: \$0.0278 per chip.

The ASIC yield figure will be available when the final sort is completed.

## Supply Chain Cost

This is the shipping cost of the material from one site to another – for example, from the wafer fab to the assembly house. And the labor cost of managing the supply chain: planning the supply chain, sending invoices, reacting to various issues or problems etc.

## Putting it All Together – Crypto ASIC Price Example

The following table shows an example of a Crypto ASIC price breakdown. For simplification reasons, we have ignored the wafer sort in this example.