ASIC Clock Jargon: Important Terms

January 21, 2015, anysilicon

Clock to an SoC is like blood to a human body. Just the way blood flows to each and every part of the body and regulates metabolism, clock reaches each and every sequential device and controls the digital events inside the SoC. There are many terms which modern designers use in relation to the clock and while building the Clock Tree, the backend team carefully monitors these. Let’s have a look at them.

• Clock Latency: Clock Latency is the general term for the delay that the clock signal takes between any two points. It can be from source (PLL) to the sink pin (Clock Pin) of registers or between any two intermediate points. Note that it is a general term and you need to know the context before making any guess about what is exactly meant when someone mentions clock latency.
• Source Insertion Delay: This refers to the clock delay from the clock origin point, which could be the PLL or maybe the IRC (Internal Reference Clock) to the clock definition point.
• Network Insertion Delay: This refers to the clock delay from the clock definition point to the sink pin of the registers.

Consider a hierarchical design where we have multiple people working on multiple partitions or the sub-modules. So, the tool would be oblivious about the “top” or any logic outside the block. The block owner would define a clock at the port of the block (as shown below). And carry out the physical design activities. He would only see the Network Insertion Delay and can only model the Source Insertion Delay for the block.

Having discusses the latency, we have now focus our attention to another important clock parameter: The Skew.

We shall now take the meaning of terms: Global Skew and Local Skew.

• Local Skew is the skew between any two related flops. By related we mean that the flops exist in the fan-in or fan-out cone of each other.
• Global Skew is the skew between any two non-related flops in the design. By non-related we mean that the two flops do not exist in the fan-out or fan-in cone of each other and hence are in a way mutually exclusive.

In the next post we would discuss the implications of big clock latency on the timing.

This is a guest post by Naman Gupta, a Static Timing Analysis (STA) engineer at a leading semiconductor company in India. To read more blogs from Naman, visit http://vlsi-soc.blogspot.in/

Image credit: ckaiserca

• Serge Mathieu

Some rules in my designs:

1- Designs are always fully synchronous.

2- All FFs in a design must be physically driven by a SINGLE CLOCK SIGNAL. This means: no ripple clocking of any FF, NO CLOCK DELAY INSERTION, NEVER EVER, no gated clock, etc. Avoid clock buffering when possible, or if buffering is mandatory, (Thousands of FFs to be clocked) clock delay (latency) should be the same for all FFs.

3- Use a clock grid distribution scheme on chip. The sole clock delay allowed is the delay caused by the metal grid itself (negligible most of the time) Clock driver shoul be centered on chip.

4- All FF use the SAME EDGE for clocking.

5-FFs are asynchronously reset at power-up, and at power-up only. FFs needing to be reset at “run time” are synchronously reset.

6- As a consequence of these rules, most FFs in a design have an Enable input: FFs do not change state when Enable is not asserted.

7- Some of these rules may know exceptions, from time to time, but very serious justification is required! (Ex: A dual clock design: a high frequency one for fast signal processing, and a lower frequency for slower events,)

Using these techniques,

A) combinatorial delays are easily managed. One does not have to analyse delays, except to verify that all delays are over within a clock period for FFs having to change their state in this single clock period, (there are generally just a few FFs having to do so) FFs changing their state at lower pace than the clock rate may have long comb. delays at their input.

B) With these techniques, gltches have no consequence. (Glitches may vary with routing, technology used, etc. Glitches on an ASCI may be different from glitches on a FPGA, But this have no consequence if one uses these techniques) (Note: Our test vectors do not compare glitches! Vectors are compared once per clock period, a few nanosec. before the active edge of the clock.)

C) Designs are easily moved to another platform (FPGA, ASIC, full custom. etc.) Placement and routing differences have generally no consequences.

Sorry, in my opinion and experience, the 14 clock buffers of the above figure should be removed.

Should anyone need more detail, feel free to contact me by email.