Dolphin Integration offers a webinar on optimizing SoC power consumption in sleep mode

May 16, 2017, anysilicon

Allowing battery-powered devices to run, without battery recharge, for years rather than months, partakes in enhancing significantly end-user satisfaction and is a key point to enabling the emergence of IoT applications. Numerous applications, such as M2M, BLE, Zigbee…, have an activity rate (duty cycle) such that the power consumption in sleep mode dominates the overall current drawn by the SoC. For such applications, the design of the “Always-On power domain” is pivotal.


To meet customer expectations, ensuring a current consumption of the Always-On power domain – incl. blocks in retention mode – not higher than 500 nA is pivotal.


After the success of our webinar presenting the recipe for a low-power SoC, our chef is back with a successful and proven recipe to ensure the lowest power consumption in sleep mode(s).


This webinar focus on the power consumption optimization of the Always-on domain based on a concrete example.


By attending this webinar, architects and designers will analyze 5 power architectures through a figure of merit, to select the most appropriate architecture with the relevant silicon IPs to reach the targeted power consumption while ensuring:

·         the smallest silicon area,

·         the lowest BoM cost.


In Mandarin, on May 18


In English:

  • on May 23 for US Time zone
  • on June 1 for EU Time zone


If you want to watch the record of our previous webinar “The proven recipe for a low-power SoC”, you can ask an access to MyDolphin.


For more information, contact Aurélie Descombes, Marketing Manager


About Dolphin Integration


Dolphin Integration contributes to “enabling low-power Systems-on-Chip” for worldwide customers – up to the major actors of the semiconductor industry – with high-density Silicon IP components best at low-power consumption.

“Foundation IPs” includes innovative libraries of standard cells, register files and memory generators as well as an ultra-low power cache controller. “Fabric IPs” of voltage regulators, Power Island Construction Kit and their control network MAESTRO™ enable to safely implement low-power SoCs with the smallest silicon area. They also star the “Feature IP”: from ultra-low power Voice Activity Detector with high-resolution converters for audio and measurement applications to power-optimized 8 or 16 and 32 bit micro-controllers.


Over 30 years of experience in the integration of silicon IP components, providing services for ASIC/SoC design and fabrication with its own EDA solutions, make Dolphin Integration a genuine one-stop shop addressing all customers’ needs for specific requests.

It is not just one more supplier of Technology, but the provider of the Dolphin Integration know-how!


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