Dual Port RAM Design – The Bit Design Goals

December 12, 2016, anysilicon

It can be asked why design a dual port memory bit?  Is this not a case of re-inventing the wheel?  Not necessarily.  Most memories are designed with speed being the main design goal.  You achieve speed by limiting that range of voltages and temperatures that the memory will operate over.  In our case, our main goals are reliability and robustness. We serve military, medical, and industrial customers whose applications frequently push the voltage and temperature limits.  We do not want the memory to be the weak link in the design.


RAM design begins with the bit. It is amazingly complex for a design that has only three types of transistors.  The bit consists of a pair of cross coupled inverters, and a pair of N-channel transmission gates that are connected to the bit lines.  In the case of a dual port memory, there are two pairs of transmission gates.


The first requirement for the bit is that all transistors be as small as possible.  This bit is replicated millions of times, so the bit area must be minimized.  The second requirement is that the bit must be writable.  The transmission gate transistor must be strong enough to pull the inverter output low enough so that the bit toggles.  A third requirement is that the bit must be readable.  That is that the transmission gate must be weak enough so that the bit line capacitance does not cause the bit to toggle when being read.  Or more specifically, approach a meta stable value that would allow noise to easily toggle the bit.  A fourth requirement specifically for the dual-port bit is that any operation on one port on a specific bit cannot interfere with the operation of the other port on that same bit.  And finally, the bit must work over all combinations of voltage, temperature and process variations.  This particular technology uses a 1.8-volt supply. Still, we would like for the memory to work with supplies of 1.5 and 1.2 volts, and over temperature ranges from -65C to +150C.  And we will try to get it to work up to 200C.


For convenience, we will refer to the inverter transistors as “P” and “N”, and the transmission gate N-channel transistor as “T”.


Writing the Bit
The worst case for writing a bit occurs when we are trying to toggle the bit while the other port is reading it.  The “T” that is setting the bit must overcome both the “P” pulling up, and the other “T” that is attached to the precharged bit line.  For simulation purposes, the bit line can be assumed to be tied to Add.  In reality, the bit line is a large capacitor that is precharged to Vdd.  Assuming that it is directly connected to Vdd is a worst-case assumption, and if the bit works with that assumption, then there will never be any problems with using the bit design in larger memories.


Reading the Bit


The danger in reading the bit is that the “T “devices will pull the low node in the memory up to a point where it can switch state in the presence of noise.  The worst case occurs when both ports are reading the same memory bit.  You have two “T” s pulling up and one “N” pulling down.  Also, the stronger the “N” device, the lower the switching threshold, which makes the situation worse.  Increasing the strength of the “P” raises the threshold, but makes it harder to write to the memory.  There are no free lunches in nature.


Running Spice

We run spice to determine the optimum sized for the “P”, “N”, and “T” transistors.  There are an almost infinite number of choices in transistor sizes, and there is not enough time to check them all.  So, the best approach is to start with a previous solution, and then vary individual transistors until an optimum is reached.  Because individual processes and process nodes vary from each other, each process will have its own optimum device size.

The layout also introduces limitations on device sizes.  To achieve a given W/L ratio, one can vary either the width or the length. Normally, the length is the process minimum, but sometimes it is better to modify the length, and allow the width to be set by layout concerns.



The Layout

Once the transistor sizes are known, the layout can be competed.  The best bit layout was determined a long time ago, so it is a matter of adjusting the sizes and spacings to match your particular process.  As an option, you can introduce a little bit of asymmetry into the layout diffusions so that the bit will tend to power up in a known state.  This is not required, but is a nice feature.

Along with the bit, we also design a dummy bit, whose output is always a zero.  This will be used in the self-timing logic.   We also have to design a set of substrate contacts that will be inserted every 8th bit.  This saves space as contrasted to including them in every bit.

Future articles will discuss the word line driver, the sense amps, and the RAM timing controls.




This is a guest post by TEKMOS  a fabless semiconductor company based in Texas.


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