Most teams don’t decide to move from FPGA to ASIC.

They get pushed there.

At the beginning of a product’s life, FPGA feels like freedom: fast iteration, low upfront cost, and a clear path to demos and early customers. But once a product starts shipping, the rules change. Unit economics matter. Power budgets become real. Supply continuity turns into a board-level concern.

This is the inflection point — the moment where staying on FPGA quietly becomes more expensive and riskier than moving to ASIC.

This article explains the five signals that experienced teams use to recognize that moment.

Signal 1: Unit cost is becoming a strategy problem

Early on, FPGA cost is “good enough.”

Later, it becomes a liability.

FPGA cost isn’t just the silicon price. It includes higher power consumption, larger boards, external memory, and margin pressure that compounds with every unit shipped.

If procurement, sales, or management are asking for real cost-down plans (not just alternate suppliers), you are no longer in a prototype mindset.

Common indicators

• You can forecast volume with reasonable confidence (even if it’s a range).
• Margin pressure increases as volume grows.
• FPGA BOM cost is blocking competitive pricing.

Signal 2: Power and thermals are limiting your roadmap

Power is often the most honest reason to move to ASIC.

FPGA power inefficiency is tolerable during development. It becomes painful in production — especially in battery-powered, thermally constrained, or fanless systems.

If you are compensating with bigger batteries, heat spreaders, throttling, or mechanical compromises, you are paying a recurring tax on every unit shipped.

Common indicators

• Battery life targets dictate product features.
• Thermal issues force enclosure or mechanical changes.
• New features are blocked by power headroom.

Quick check

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Signal 3: You’ve hit a performance ceiling optimization can’t fix

Teams usually try multiple FPGA optimization cycles before considering ASIC: tighter RTL, better constraints, faster memory, more parallelism.

Sometimes it works.

Sometimes you discover the limitation is the platform itself.

ASIC enables architectural freedom — custom datapaths, tailored memory hierarchies, hard macros, and predictable timing — but only if your requirements are stable.

Common indicators

• Timing closure dominates development cycles.
• Performance targets are missed despite multiple optimization attempts.
• Deterministic latency or throughput is becoming critical.

Signal 4: Longevity and supply continuity are now non-negotiable

When customers expect 10+ years of availability, FPGA and off-the-shelf parts can become a risk.

ASIC doesn’t magically eliminate supply issues, but it gives you control: mature nodes, long-term manufacturing plans, and lifecycle ownership.

This signal often appears later — but when it does, it tends to be decisive.

Common indicators

• Longevity commitments appear in contracts.
• Lead times or discontinuations have already caused pain.
• Redesign cost outweighs the cost of custom silicon.

Signal 5: Integration pressure is increasing

As products mature, integration pressure grows:

• Fewer components
• Smaller boards
• Higher reliability
• Lower assembly risk

Glue logic, external devices, and board complexity accumulate quietly until manufacturing, yield, or form factor forces a change.

ASIC is often the cleanest path to integration once the architecture stabilizes.

Common indicators

• Board routing complexity is slowing releases.
• Manufacturing yield issues trace back to component count.
• Form factor limits future versions of the product.

The three traps that delay the decision

Even when the signals are obvious, teams often delay. The same traps appear again and again:

1. “We’ll optimize the FPGA one more time.”
   
   Fine once. Dangerous when it becomes the default answer.
2. “ASIC is only for big companies.”
   
   In reality, ASIC viability depends on economics (volume + lifetime) and readiness — not company size.
3. “We need perfect specs before talking to anyone.”
   
   You don’t need perfect specs. You need clarity on risk, volume, and priorities.

What to do next (practical)

If one or more signals resonate, don’t jump straight into an ASIC commitment.

The fastest next step is to make the decision explicit, not emotional.

• Check whether ASIC makes sense now, later, or not at all
• Identify what is missing (volume confidence, NRE expectation, spec maturity)
• Decide your next milestone with intention

 Next step

Not sure if you’ve reached the inflection point?

Run the 2-minute ASIC or Not? Decision Wizard to get a clear direction and next steps.