P&R team management:

Developing and distributing the design flow for power analysis on a low power IC device.
Performing runtime saving, quality improvement, power saving tests using various PnR options and PG mesh structures on blocks.
Interacting with vendors to solve issues.
Documenting design flows and checklists for future use by engineering teams.
Expertise of ASIC design flow from RTL to GDSII (PnR, STA, Power Analyzes, Physical verification)
Top & block level physical verification and debug
Expertise on Low Power chips with hierarchical design
Developing methodology and automation tools with proven quality
Have done 5 chips tape-outs

Layout team management:

Validation and QA flows for memory compilers
Layout design of SRAM Memory compilers, logic cell libraries