2512007

Highly experienced digital SoC CTS, timing closure and layout engineer. Expertise in RTL to gdsii design, troubleshooting and customer support. Particular expertise in clock implementation (synthesis, multi-source CTS and mesh) and with the Cadence Innovus flow.

Based in UK with international experience working in ASIC, SoC and EDA/IP companies from start-ups to multinationals.

Persistent, resourceful and thorough.