Skilled with low-power design methodologies / power intent from simple clock gating or VDD reduction to minimize dynamic and static power, to advanced methods such as Cadence CPF and Synopsys UPF to implement block-based power off with data retention, variable VDD, low-power standby with full state retention, power on demand, and dynamic and adaptive voltage and frequency scaling.


Experienced with SoC (hierarchical block-based or flat), constraint development and verification (CDC), formal verification, high-speed interfaces and clock trees and H-mesh clock networks, multi-mode multi-corner timing closure (MMMC), signal integrity, nanometer CMOS processes (16nm, 20/22nm, 28nm, 40nm, 55nm, 90nm), package design including modeling flip-chip & area I/O, and mixed-signal design including specification, deliverable QC, and schedule management.


Expert in UNIX/Linux, Perl, TCL, Python, Verilog, VCS, NCVerilog (IUS), Formality, Conformal, Calibre, SPICE, ANSYS/Apache. Also skilled at rapidly mastering new EDA tools and design flows, accelerating development schedules, and creative problem solving.