Principal Digital Designer, RTL Expert, Front-end flow.


Involved in the ASIC System-on-Chip development in all the phases: IP modules RTL development from the scratch (VHDL, Verilog, Systemverilog), sub-system & top-level implementation (ARM micro & peripherals), validation. A constant eye on Low-Power, High-Speed, Low-Area optimization.


Used to work in multi-cultural/language project teams, collaborating with Verification & Backend teams


Strong problem solving & organized approach attitude skills, pro-active behaviour.