Belgium
– Design of digital blocks for mixed-signal ASICs using VHDL and Verilog
– Develop the required testbench, verification models and testcases using UVM
– Create verification test plans based on specifications
– Perform functional coverage, assertion coverage, and code coverage
– Signoff activities: formality, STA, gate-level simulations
– Experience with ARM Cortex-M0 and M4 processors
– Experience with SPI, I2C, UART and AHB interfaces
– Experience with System Verilog assertions
– Experience with Linting, CDC, RDC
– Experience with low power design techniques
– Power aware simulation with UPF