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How to Get the Most Out of Fusion Compiler

The field of chip design is constantly evolving, and Electronic Design Automation (EDA) tools have become indispensable for designing complex integrated circuits. These tools offer a wide range of functionalities to streamline the design process, optimize performance, and ensure manufacturability. However, using EDA tools efficiently requires a solid understanding of their capabilities and effective utilization strategies. In this article, we will explore various tips to help you harness the potential of Synopsys’ Fusion Compiler for successful physical implementation and layout of your chip.

 

 

Understand the Capabilities and Limitations of Fusion Compiler

 

  • It is important to understand the capabilities of FC by reading the documentation, attending training sessions and exploring online resources to learn about the features of the tool. Synopsys may also be able to provide some results on known designs and provide with a comparison of key quality metrics like frequency, power, area and run time between different tools (like FC v/s ICC v/s ICC2) or different tool versions.
  • Any given EDA tool may also have some limitations which might even be advertised as strengths. It is important for designers to understand these limitations well so that they can plan their custom solutions upfront. This might be a blessing in disguise as tool limitations usually spark off innovation and this innovation can differentiate one design house from the other, in terms of achieving the best possible QoR with same technology and using the same tool set as their competitors. Limitations can manifest themselves in the form of excessive run time, or sub-optimal optimization in a given scenario or simply lack of a new feature that other similar tools in the industry may be offering.
  • Synopsys R&D is eager to understand these limitations and improve their tools to cater to a broad range of use-cases and applications. This is where design houses and the EDA companies need to work together to improve the tools, flows and methodologies.

 

Document Best Known Methodologies

 

  • It is important to document all the best-known methodologies to prevent teams from “re-inventing the wheel” a few years down the line.
  • While Fusion Compiler has also evolved during this time, having a document of best-known practices handy can serve as a good starting point and therefore save precious time for the designers.
  • Documented material can also serve as training and onboarding resource for new designers and accelerate the learning curve.
  • Documenting methodologies provide a basis for continuous improvement in chip design processes by enabling a cycle of iterative improvement. It also makes it easier to identify areas for improvement and propose enhancements to existing methodologies.

 

Gaining insights into FC’s Internal Algorithms

 

While internal algorithms of Fusion Compiler, or any other tool for that matter, are proprietary information, designers tend to gain some insights by:

 

  • Running through multiple experiments and analyzing the behavior of the tool.
  • Reading academic research papers to understand other known algorithms for similar problems.
  • Discussing with their application engineers on how to tune the tool to cater to their specific use case.

 

These insights can help designers tune their recipe to achieve the optimal QoR without running too many experiments and without spending too many resources. With respect to the physical implementation where designers are always dealing with multiple trade-offs, firing off experiments by changing one or more variables in a controlled manner can help map the changes in the QoR to exact recipe changes.

 

Scan the Log Files

 

The Fusion compiler log files contain a vast gamut of information highlighting

 

  • Warning and error messages that need attention of the designers.
  • Intermediate results that designers can prefetch to make corrections and experiment with alternate recipes rather than waiting for their runs to complete.
  • Some insights into the internal algorithms or steps of complex optimization commands.

 

Designers can learn so much about their design and the tool itself by carefully checking the log file.

 

Monitor the Run times, Memory Usage and Core Requirements for your Job

 

Designers should carefully monitor the peak and the average memory requirements for their jobs. The memory requirements are usually a function of:

 

  • Size of the design: A bigger design, either in terms of bigger layout, more gates to process, more modules to simulate, or more tests to perform would translate into higher memory requirements and potentially longer run times.
  • Design QoR: If the design happens to be broken in terms of the QoR that it is trying to optimize, the run times tend to be higher.

 

Designers need to choose a sweet spot in terms of appropriate number of cores and memory requested to prevent seeing their jobs running out of memory or taking a long time to complete which can translate into longer turn-around-time (TAT). Fusion Compiler has settings to optimize performance and speed up the design process. Designers should configure FC to take advantage of parallel processing, multicore support, and other optimization options.  

 

 

The above curve highlights the trade-off between the run time of a job and the number of cores requested. For an initial increase in the number of cores, the run times usually drop exponentially, and saturates for any further number of cores requested. Designers should aim to hit the knee of the below curve to achieve maximum throughput and efficiency.

 

Utilize Design Reuse and IP Blocks

 

Synopsys often provides libraries of pre-designed components like standard cell or memory macros, and intellectual property (IP) blocks. Utilizing these resources to accelerate your chip design process leads to faster time-to-market. Design reuse not only saves time but also enhances reliability by utilizing well-tested and validated components, and therefore reduce the risk of errors or design flaws. Explore the available libraries, understand their compatibility, and integrate them into your design when appropriate. Design reuse allows designers to focus their efforts and resources on the unique and innovative aspects of their design and therefore bring differentiation to their products, add value and competitive advantage.

 

 

Familiarize Yourself with Fusion Compiler

 

Take the time to thoroughly understand Fusion Compiler. Read the documentation, attend training sessions, and explore tutorials to grasp its features, capabilities, and limitations. Becoming proficient in navigating FC’s user interface is essential for maximizing productivity. Spend time learning FC’s features, shortcuts, and customization options. Familiarize yourself with the various menus, toolbars, and windows that facilitate different design tasks. Efficiency in using Fusion Compiler interface will save time and enhance your overall design experience.

 

Stay Updated!

 

The field of chip design and EDA tools evolve rapidly. Stay updated with the latest trends, tool releases, and advancements in chip design methodologies. Engage with Synopsys’ community forums, attend conferences, and participate in webinars to expand your knowledge base. This continuous learning will help you leverage new features and techniques to improve your design process. Also, it is important not to put all your eggs in one basket. Designers should always focus on the fundamentals that drive the implementation of the tool engines. The fundamentals stay constant across EDA vendors, though the final results, elegance of the GUI or even suite of various available features may vary from one vendor to another. . Synopsys also organizes SNUG (Synopsys User Group) conferences inviting all the customer design houses to share their innovations using their tools. Attending these conferences help expose designers to broad range of applications and use-cases and there is always plenty of stuff to learn and apply for your particular application. Perusing SNUG proceedings is another great way to brush up your technical skills and get more insights into a topic through practical examples.

 

Seek Support from Synopsys

 

Synopsys offer comprehensive support resources to help users overcome challenges and maximize all of their tool’s potential. Take advantage of tutorials, user guides, online forums, and direct support channels offered by the vendor. Reach out to their technical support team when encountering issues or seeking guidance. The vendor’s expertise can provide invaluable insights and solutions to optimize your chip design process.

 

Utilize Design Automation Scripts

 

Synopsys often provides scripting interfaces or reference methodologies (RM) that allow designers to automate repetitive tasks or create custom design flows. These reference methodologies also serve a good starting point to develop the flow that is caters for specific needs. The design automation scripts help streamline your design process, improve productivity and reduce human errors. These scripts can be written in languages like Tcl, Perl, or Python depending on the use-case.

 

Expertise with the Fusion Compiler GUI

 

The Fusion Compiler Graphical User Interface (GUI) provides an easy way to visualize the design, the design components and also various quality metrics in form of pictures. GUI makes the identification of issues more efficient, particularly for big designs without relying on summary reports that may obfuscate the complete picture.

 

Below are examples of the FC’s GUI capabilities. The layout window helps visualize the design components and their placement.

 

 

Fusion Compiler also allows designers to generate various maps like the cell density maps, the global route congestion map or the wire utilization map etc. Designers can zoom into any region of interest to understand the issues and improve the recipe.

 

 

 

Correlation of FC Results with Signoff tools

 

Lastly, it is important for designers to ensure their QoR at every step is matching well with other signoff tools like the timing signoff tool, the physical verification tools and also the IR drop simulation tools. Some parameters can be tweaked to achieve better correlation, and this will help produce a cleaner design upfront.

 

Summary

 

Physical implementation tools are indispensable in the chip design process, as they bridge the gap between the logical representation and the physical representation of a design. Fusion Compiler is the industry leading tool for physical implementation. With these tips in mind, you will be well-equipped to navigate Fusion Compiler and achieve successful outcomes in your projects.

 

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