ASIC and Logic Design Engineering Manager [Teradyne, North Reading]

Teradyne is a global leader in test and automation solutions, ensuring the reliability of electronic devices through innovative technologies. We are committed to fostering a diverse and inclusive work environment that empowers our employees to excel and innovate. We are currently seeking a Logic Design Manager to lead a team in designing and verifying FPGAs for our Compute Test Division's next-generation products.

Responsibilities:

• Lead a team of 4-6 engineers in FPGA design and verification.
• Manage multiple FPGA or digital IP development projects simultaneously.
• Collaborate with other engineering disciplines to meet product requirements.
• Plan and track project schedules and budgets.
• Oversee project staffing levels, including full-time and contract resources.
• Represent the FPGA team in project core teams and program reviews.
• Contribute to FPGA implementation as needed.
• Provide technical support for hardware sustaining issues.
• Set goals, coach, and manage compensation for the team.
• Drive process improvement initiatives within the FPGA team.

Qualifications:

• BSEE or MSEE with 12+ years of relevant experience in Digital FPGA design and integration.
• Minimum of 5 years as an FPGA/ASIC project lead.
• Extensive experience coding RTL (Verilog preferred).
• Experience with digital simulation tools (Cadence preferred).
• Familiarity with PCIe, DDR3/4/5, AXI, ethernet, SPI, SERDES.

Skills:

• Experience with AMD or Altera FPGAs and development tools (Vivado/Quartus).
• Proficient in digital design quality tools (e.g., LINT, CDC).
• Familiarity with bug tracking tools (e.g., Jira) and source control systems (e.g., Git).
• Knowledge of digital verification tools and methodologies (preferably UVM).
• Excellent presentation and communication skills.