ASIC Architect

Datavault AI, along with its subsidiary Event Citadel, is seeking a Full-Time ASIC Architect to design and optimize high-performance semiconductor chip architectures. The role involves translating product requirements into technical specifications and leading cross-functional efforts in IP integration and verification. The successful candidate will contribute to the development of third-generation technology for the WiSA Acoustics Division, focusing on balancing cost and performance for high-volume, high-performance products.

Responsibilities:

• Create chip-level and subsystem specifications, including memory hierarchy and high-speed interfaces.
• Partner with an IP Vendor to expedite ASIC development.
• Develop performance models and simulators to optimize Power, Performance, Area, and Cost (PPAC).
• Author detailed technical documents outlining microarchitecture and design constraints.
• Collaborate with RTL designers, verification, and software teams to ensure feasibility and guide implementation.
• Analyze design trade-offs to balance performance with power and area constraints.
• Mentor junior engineers and promote best practices in design and verification.

Qualifications:

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related fields.
• Significant experience (6+ years) in silicon architecture, performance modeling, or design.
• Strong skills in C++, Python, System Verilog, and architectural modeling tools.
• Deep understanding of computer architecture, AI/ML accelerator design, or GPU architecture.
• Excellent communication skills for documenting specifications and negotiating technical trade-offs.

Skills:

• Silicon architecture
• Performance modeling
• C++ programming
• Python programming
• System Verilog
• Architectural modeling tools
• Computer architecture knowledge
• AI/ML accelerator design
• GPU architecture understanding