Published Date: February 18, 2026
Annapurna Labs (U.S.) Inc., Cupertino, CA
Job Description:
Join the Cloud-Scale Machine Learning Acceleration team at AWS as an ASIC Design Engineer, where you'll design and optimize hardware for our data centers, including the AWS Inferentia server. This role focuses on developing high-performance, power-efficient RTL designs while collaborating with cross-functional teams to ensure design integrity and quality.
Responsibilities:
- Develop and implement high-performance, area and power-efficient RTL designs to meet project specifications.
- Conduct in-depth analysis of designs and architectures to optimize trade-offs between features, power consumption, performance, and area requirements.
- Create microarchitectures and implement SystemVerilog RTL, delivering synthesis and timing-clean designs with appropriate constraints.
- Execute lint and clock domain crossing quality checks to ensure design integrity.
- Collaborate closely with architects, designers, verification specialists, and validation teams.
Qualifications:
- Bachelor's degree or equivalent in a relevant field.
- 3+ years of design or architecture experience in new and existing systems.
Skills:
- Proficiency in SystemVerilog.
- Strong analytical and problem-solving skills.
- Familiarity with interconnects, DMAs, memory sub-systems, and system-level architectures.
