ASIC Engineer, Design Verification

Meta is seeking an experienced ASIC Design Verification Engineer to join its Infrastructure organization, focusing on developing IP and System On Chip (SoC) solutions for data center applications. This role involves working within an agile team to ensure the verification closure of design modules, utilizing various methodologies including UVM, Formal, and Emulation to deliver high-quality designs.

Responsibilities:

• Define and implement IP/SoC verification plans and build verification test benches.
• Develop functional tests based on the verification test plan.
• Drive Design Verification to closure based on defined metrics, including functional and code coverage.
• Debug and resolve functional failures in collaboration with the Design team.
• Collaborate with cross-functional teams to ensure high design quality.
• Implement continuous improvements in Design Verification using the latest methodologies and tools.

Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field.
• 6+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification.
• 6+ years of experience in IP/sub-system and/or SoC level verification using SystemVerilog UVM/OVM methodologies.
• Experience with EDA tools and scripting languages (Python, TCL, Perl, Shell).

Skills:

• Experience with revision control systems (Mercurial, Git, SVN).
• Verification of ARM/RISC-V based sub-systems or SoCs.
• Functional verification including SV Assertions, Formal, and Emulation.
• Development of UVM based verification environments from scratch.
• Architecting and implementing Design Verification infrastructure.
• Verification of high-speed interfaces (PCIe, RoCE, Ethernet, DDR, HBM).
• Micro-architectural performance verification.
• Experience verifying GPU/CPU designs.
• Design verification of data-center applications (Video, AI/ML, Networking).
• Building relationships with cross-functional teams.