ASIC Implementation Lead

Join Google as an Implementation Technical Lead (TL) to shape the future of AI/ML hardware acceleration. This role focuses on driving cutting-edge TPU technology, ensuring the physical realization of next-generation custom silicon, and leading cross-functional teams through the full tape-out cycle. You will be instrumental in delivering high-quality SoC systems that power Google's most demanding applications.

Responsibilities:

• Drive technical decisions and synchronization across all implementation domains (physical design, package, power, SI/PI, DFT, etc.), resolving cross-functional issues that impact chip delivery.
• Own the physical implementation of the entire chip, ensuring the final packaged silicon meets all performance, power, area, thermal, yield, and reliability goals.
• Identify critical blocking issues and implementation risks early, developing and executing mitigation strategies to protect the program schedule and quality.
• Manage technical interactions with ASIC partners and external vendors to ensure their deliverables align strictly with chip requirements and milestones.
• Define the framework for implementation execution, including setting technical directions, establishing milestone criteria, and innovating methodologies.

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in silicon implementation with a focus on SoC or ASIC development.
• Experience leading cross-functional teams through the full tape-out cycle, from architecture to GDSII.
• Experience with advanced process nodes, packaging technologies, and trade-offs between PPA, thermal, and signal integrity.
• Experience managing technical relationships with external vendors, ASIC partners, or foundries.

Skills:

• Ability to drive high-frequency/low-power chips to production with first-pass silicon success.
• Experience with Customer Owned Tooling (COT) design models and their specific issues compared to traditional ASIC flows.
• Experience defining implementation roadmaps and influencing decisions at the system and architecture level.
• Ability to articulate technical risks and status to executive management and cross-functional stakeholders.