ASIC RTL Design Engineer, ML Accelerators, University Graduate

Join Google's AI and Infrastructure team as an ASIC Design Engineer, where you'll contribute to the development of cutting-edge TPU technology that powers AI/ML applications. This role involves designing and verifying complex digital designs, focusing on custom silicon solutions for data center accelerators.

Responsibilities:

• Develop SystemVerilog RTL to implement logic for ASIC products.
• Create and review design microarchitecture specifications.
• Collaborate with Design Validation (DV) teams to create test plans for verifying and debugging design RTL.
• Work with Physical Design teams to ensure designs meet physical requirements and achieve timing closure.

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• Experience with digital design basics, including synchronous and asynchronous logic, state machines, and bus protocols.
• Experience with Verilog or SystemVerilog.
• Master's degree in a related field is preferred.
• Experience optimizing designs for performance, power, or area is preferred.
• Proficiency in scripting languages such as Python or Perl is preferred.

Skills:

• Digital design fundamentals
• Verilog/SystemVerilog proficiency
• Design validation and debugging
• Physical design collaboration
• Scripting in Python or Perl