Design Engineer [Low Power]

Qualcomm Atheros, Inc. is seeking an experienced ASIC Design Engineer to join its Integrated Wireless Technology team. The role focuses on developing low power micro-architecture and design for WiFi technology, SOC design, and power reduction techniques. The candidate will be involved in the full ASIC development process, from specification to post-silicon bring-up, and will work closely with the verification team.

Responsibilities:

• Develop technical specifications from architectural and systems requirements.
• Deliver detailed low power micro-architecture and design.
• Collaborate with the verification team to create verification plans and participate in debugging phases.
• Own design through the full ASIC development process including specification, RTL implementation, verification, synthesis, timing closure, emulation, and post-silicon bring-up.
• Conduct silicon power measurements, silicon debug, and power correlation.
• Perform full chip debug design using ARM IPs.

Qualifications:

• Bachelor's degree in Science, Engineering, or related field with 6+ years of ASIC design experience, or a Master's degree with 5+ years, or a PhD with 4+ years.
• Experience in ASIC design, verification, validation, and integration.

Skills:

• 7+ years of working experience in ASIC Design.
• 2+ years of experience in low power micro-architecture and design.
• Proficiency in power intent/implementation, power optimization, and power estimation.
• Experience in silicon bring-up and debug.
• Familiarity with SoC micro-architecture, multi-domain clocking, and AMBA bus protocols (AHB, APB, AXI preferred).
• Experience with ARM IP based full chip debug, PCIE/USB peripherals, and CPU subsystem-based design.