Design Verification Engineer

Join Project Kuiper, an initiative aimed at launching a constellation of Low Earth Orbit satellites to provide high-speed broadband connectivity to underserved communities globally. We are seeking a skilled engineer to define and implement digital chip SOCs for communications via these satellites and Amazon gateways, contributing to a groundbreaking wireless solution.

Responsibilities:

• Implement a state-of-the-art verification environment for testing RTL against reference Matlab/C models.
• Develop detailed test plans, write tests, run regressions, collect coverage matrices, and report progress.
• Participate in the validation of ASIC implementations in Verilog/SystemVerilog.
• Collaborate with design and communication systems teams for system-level verification using UVM test benches.
• Create a highly automated environment for running regressions and maintaining database organization.

Qualifications:

• Bachelor's degree in Electrical/Communications Engineering, Computer Science, or related field, or equivalent experience.
• 2+ years in verification, preferably in communication systems.
• 2+ years of experience with UVM.

Skills:

• Master's or Ph.D. in Electrical/Communications Engineering (preferred).
• 3+ years in digital verification, preferably in communication systems.
• Familiarity with Matlab and modem design verification.
• Experience in System C, C, or Matlab model development or DV integration.
• Knowledge of formal verification techniques.
• Strong written and verbal communication skills.