DFT [Design For Test] Engineer

Etched is pioneering an AI inference system designed specifically for transformers, achieving over 10x higher performance and significantly reduced costs and latency compared to traditional solutions. With substantial backing from top-tier investors and a team of leading engineers, Etched is transforming the infrastructure for the rapidly growing AI industry.

Responsibilities:

• Develop and implement robust Design for Test (DFT) architectures for ASIC and SoC designs to enhance test coverage and fault isolation.
• Integrate industry-standard DFT methodologies such as scan insertion, boundary scan, Built-In Self-Test (BIST), and Memory BIST (MBIST).
• Collaborate with design and verification teams to ensure DFT requirements are consistently addressed throughout the design cycle.
• Analyze test results and silicon debug data to provide feedback and drive improvements in coverage, yield, and reliability.
• Create and execute comprehensive DFT verification plans to validate DFT features.
• Apply simulation-based and formal verification techniques to ensure DFT logic correctness.
• Conduct internal DFT audits and design reviews to identify and resolve gaps in testability.
• Support silicon bring-up, debug, and failure analysis during post-silicon validation.
• Partner with test engineering teams to develop and optimize Automated Test Equipment (ATE) programs for production.
• Generate production-quality test patterns and ensure robust failure analysis capability.
• Collaborate with manufacturing and quality teams to implement data-driven test process improvements.
• Ensure test strategies align with product milestones and quality targets.
• Author and maintain documentation for DFT architecture, test plans, and procedures.
• Share best practices through training sessions and mentorship to enhance DFT awareness.
• Stay current with emerging DFT technologies and industry trends.

Qualifications:

• 10+ years of experience in DFT engineering with successful test implementations for ASIC or SoC products.
• Deep understanding of digital design, verification methodologies, and DFT practices.
• Proficiency in System Verilog and EDA tools (e.g., Synopsys DFT Compiler, Cadence Encounter Test).
• Scripting and automation experience using Python, Perl, or TCL.
• Track record of leading DFT initiatives in high-performance or high-volume silicon environments.
• Strong analytical and debugging skills to resolve complex testability issues.
• Excellent communication and collaboration abilities.
• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field (Master’s preferred).

Skills:

• Mixed-signal DFT methodologies and integration of analog testability into SoC workflows.
• Familiarity with industry standards such as IEEE 1149.1 (JTAG) and IEEE 1500.
• Experience in yield analysis and contributions to test cost reduction and quality improvement programs.