Join UST as an FPGA Design Verification Engineer, where you will play a crucial role in verifying complex FPGA designs to ensure their functionality, performance, and reliability. Collaborating closely with design engineers, you will develop and execute verification plans, create test benches using industry-standard methodologies like UVM and System Verilog, and debug issues to enhance product quality. Your expertise in FPGA, ASIC, and RTL design principles, along with proficiency in verification tools, will be essential in this dynamic environment. With a strong foundation in electrical or computer engineering and over 10 years of experience in FPGA design or verification, you will contribute to innovative solutions that transform lives through technology. UST offers a competitive compensation range of $182,000-$273,000, along with comprehensive benefits including paid vacation, medical insurance, and a 401 plan. Join us in making a lasting impact on clients and communities worldwide.
