Lead Hardware Design Engineer – Power Delivery

PowerLattice is a pioneering semiconductor startup focused on revolutionizing high-performance chip power delivery through innovative chiplet solutions. We are seeking a Lead Hardware Design Engineer - Power Delivery to lead the development of our power delivery hardware architecture, ensuring our technology meets the needs of tier-one customers.

Responsibilities:

• Lead the design and development of complex hardware platforms, including schematic entry, PCB layout, and BOM management.
• Drive high-density, multi-layer PCB design focused on Power Delivery Networks (PDN).
• Define hardware architectures for reference platforms and validation boards, integrating multi-chiplet SoC solutions and high-performance power converters.
• Assist customers in optimizing their PDN designs using PowerLattice’s design kits and proprietary chiplet technology.
• Lead the physical bring-up and debugging of complex subsystems, utilizing advanced instrumentation to resolve power/reset timing and silicon anomalies.
• Act as a mentor and project lead, coordinating with cross-functional teams in SIPI, packaging, and manufacturing.

Qualifications:

• 10+ years of experience in hardware design, specifically in power integrity and high-performance SoC platforms.
• Extensive hands-on experience with Schematic Capture and PCB Design tools (e.g., Cadence Allegro, OrCAD, or Altium Designer).
• Deep proficiency in extracting, building, and validating electrical models for SoC packages and power delivery networks.
• Strong understanding of package-level SI/PI, including substrates, interposers, and 2.5D/3D packaging technologies.
• Excellent verbal and written communication skills.

Skills:

• Expertise in hardware design and power integrity.
• Proficient in PCB design tools and methodologies.
• Strong analytical and problem-solving skills in hardware development.
• Ability to mentor and lead cross-functional teams.