Senior ASIC Physical Design Engineer

Join Google as an ASIC Physical Design Engineer, where you'll shape the future of AI/ML hardware acceleration by driving cutting-edge TPU technology. Collaborate with teams to develop custom silicon solutions that power Google's most demanding applications, contributing to innovations that impact millions worldwide.

Responsibilities:

• Participate in the Physical Design of complex blocks.
• Contribute to the design and closure of the full chip and individual blocks from RTL-to-GDS.
• Collaborate with internal logic and teams to achieve optimal Power/Performance Analysis (PPA).
• Conduct feasibility studies for new microarchitectures and optimize runs for finished RTL.

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 7 years of experience with physical design from RTL to GDSII, including floorplanning, place and route, and timing closure.
• Experience in Python, Tcl, or Perl scripting.

Skills:

• Experience working with external partners on Physical Design closure.
• Experience in Static Timing Analysis (STA) and defining timing corners, margins, and derates.
• Familiarity with Synopsys/Cadence PnR tools.
• Knowledge of backend flows such as LEC, PI/SI, DRC/LVS.
• Understanding of DFT including Scan, MBIST, and LBIST.
• Knowledge of performance, power, and area (PPA) trade-offs.