Senior DFT Engineer – LPU

NVIDIA is seeking a Senior DFT Engineer to lead the development and implementation of Design for Test (DFT) architecture for next-generation AI chips. This role involves collaboration with cross-functional teams to apply innovative DFT methodologies, ensuring high-quality products in a diverse and supportive environment.

Responsibilities:

• Define and implement SCAN, MBIST, and JTAG debug structures using advanced DFT techniques.
• Create ATPG and MBIST test vectors.
• Build DFT timing constraints and collaborate with Physical Design and STA sign-off teams for timing closure in DFT mode.
• Work with the post-silicon team to bring up test patterns on silicon.
• Collaborate with the CAD methodology team to introduce AI-driven optimizations for DFT implementation.

Qualifications:

• Bachelor's or M.S. in Computer Engineering or Electrical Engineering (or equivalent experience).
• 5+ years of industry experience in DFT for high-performance ASICs.

Skills:

• Practical experience with SCAN/MBIST/Test generation tools for large SoC/ASIC.
• Expertise in DFT techniques such as ATPG, test pattern translation, yield learning, scan compression, MBIST, IEEE 1500 standard, and LBIST.
• Familiarity with ATPG Streaming SCAN Network (SSN) implementation.
• Experience with UDFMs like Cell Aware and Small Delay Defect.
• Strong coding skills in Tcl and Python.
• Excellent interpersonal and organizational skills.