February 26, 2024 — Noesis Technologies has announced today the immediate availability of its ntFFT_UHS IP Core that implements a customized FFT/IFFT programmable fixed point (Decimation in Frequency – DIF) transform processor, supporting low latency, streaming, ultra-parallel complex samples per clock cycle in natural order. Input, internal and output 2’s complement fixed point precision are fully configurable before IP synthesis. Radix-2, Radix-4 or Mixed-Radix design may be selected with parallel butterflies deployment, depending on the implemented transform sizes. Each stage features its own permutation network buffer, implemented optionally as either Register File or BRAM primitives. Twiddle factors fixed-point precision is selected via parameterization and the values are pre-calculated and stored in small distributed LUTs next to the respective butterflies, using a scalable design methodology. The permutation of each buffer stage is necessarily custom-made, since it is dependent on the parallel samples per clock cycle configuration and the supported FFT transform sizes. An optional Circular Shift buffer can be instantiated for those applications that need to correct a detected Carrier Frequency Offset in the frequency domain (FFT), with range of circular shifts correction relevant to both the FFT transform size and the parallel samples per clock cycle. Additional Overlap-Save (OLS) method wrappers may be provided to support real time high bandwidth filtering applications.
The ntFFT_UHS IP core can be used in a variety of applications, including Communication Systems, Spectrum Analysis, OFDM modems, Image processing, Streaming Filtering applications, Defense Receivers and Signal Monitoring, Medical and Scientific Instruments.
Availability
The ntFFT_UHS is available under a flexible licensing scheme as parameterizable VHDL or Verilog source code or as a fixed netlist in various FPGA target technologies.
About Noesis Technologies P.C. (www.noesis-tech.com)
Noesis Technologies, P.C. is a leading Silicon IP Core provider in hardware acceleration computing engines enabling high performance data connectivity solutions for radar, lidar and communications processing. Our hardware accelerator IP solutions allow telecom system developers to significantly off load demanding tasks from the CPU and to drastically decrease execution time thus boosting the overall system performance. Our IP cores present an industry leading combination of high performance, low power and low die-area, as well as easy customization for adaptability to a wide range of applications. Noesis offers a complete portfolio of Baseband PHY layer hardware accelerators that can be used in the markets of IoT, Smart Home/Grid, WiFi, Gigabit Ethernet, Security & Defense, Automotive & Consumer Electronics. Noesis IP cores have been licensed to many customers worldwide ranging from tier-one companies to innovative start-ups and have been integrated into SoC, ASIC and FPGA designs for various end-products in Telecom, Défense, Industrial, and Space sector. Noesis Technologies is headquartered at Patras Science Park, GR 26504 Patras, Greece and has offices at USA, Israel, India, China and Taiwan. For more information please visit www.noesis-tech.com
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