RISC-V: Reducing Risk for both the Consumer and the Supplier

July 12, 2017, anysilicon

Last week was the Linley Processors Conference held in Santa Clara, CA. where vendors announced new products and technical details about new network architectures, security implementations, and novel memory devices were disclosed. Session 8 was titled “Open Instruction Sets” and featured a “pro” presentation by Krste Asanović, Professor, University of California, Berkeley and Chairman, RISC-V foundation, followed by a “con” presentation by Markus Levy, President, EEMBC. A noticeable chuckle from the audience was heard when Markus preceded his presentation by saying that “about 80% of what I’m going to present I don’t necessarily agree with”. Seems Markus was coerced by the Linley Group into making an attempt at convincing us that open source solutions “Costs You Somewhere”. And it definitely showed that Markus was only about 20% convinced – his points were rather weak IMHO.


The “pro” presentation was quite the opposite – pragmatic, factual, and chock full of examples. Krste showed a chart showing how open source solutions have been adopted throughout the tech industry – except by processor vendors who have always espoused the benefits of a proprietary instruction set architecture (ISA). As the CEO of an embedded processor IP company, I am willing to admit that the benefits of a proprietary ISA are one-sided – and that benefit is on our side, not the customers unfortunately.



RISC-V changes customer disadvantages into mutually beneficial terms and levels the playing field for all embedded processor IP companies in two important ways:

  1. Customers can delay selecting an embedded processor IP vendor until later in the design cycle. Why is this a benefit for the customer? Because when embedded IP processor vendors bid for their business, customers get a better deal. As it works now, customers select an embedded processor IP vendor before the design project starts – and the IP vendor knows the customer is locked-in. Does that affect pricing? Tech support? Partnering to create compelling semi-custom solutions? Customers tell us “yes – very much so”. Having the customer locked-in is a huge advantage to market leaders like ARM and MIPs.RISC-V allows design teams to use any RISC-V vendor’s tools and processor IP without making a vendor selection, knowing they can easily switch vendors at any time. Is it a big deal to switch from one IDE to another if they are all Eclipse based? I’m told it’s like switching email applications – not a problem and takes little time.And as customer’s design project matures, they’ll have more accurate knowledge about their actual processing requirements and their embedded software will become more stable. This allows customers to make more INTELLIGENT IP vendor selections, providing them with better processor IP with better purchasing terms and better technical support.With RISC-V, customers are no longer locked-into any IP vendor. With freedom to select the optimal processor with the best business conditions, they’re products and company will benefit.
  2. Customers no longer need to be concerned with the stability of their IP vendor when using RISC-V. We hear from potential customers all the time that they’re concerned with using a small startup company’s IP for fear the startup will go out of business. It’s much like the old saying “no one gets fired for buying IBM computers” … yet, not many folks these days are buying IBM computers! With the acquisition of ARM, it’s actually an ironic twist. For many years customers have told us they can’t take a risk using a startup’s IP – and now, they are at risk because a potential competitor has purchased the industry’s largest vendor, ARM!RISC-V allows customers to select any embedded processor IP vendor, large or small, knowing their embedded software is portable in case the vendor goes out of business. It’s a HUGE benefit for Codasip as we no longer are handicapped because of our age and size. Codasip has RISC-V cores available today – and there’s no risk in using them!


Free and open standards have arrived for processor IP … finally. I encourage you to consider taking advantage of an independent ISA like RISC-V. And you can start today – without being locked-in. Get in touch and we’ll be happy to support you with our Codix-BK processor cores which are customizable and extensible implementations of the RISC-V ISA.


About The Author 

Dr. Karel Masarik is the CEO, CTO, and co-founder of Codasip, overseeing its technology development, strategic positioning, and commercial operations. Dr. Masarik has a PhD degree in Computer Science from the Brno University of Technology, in Brno, Czech Republic.

Recent Stories