ASIC Physical Design

ASIC Physical design is sometimes called “back-end design” because it follows the “front-end” which is generally the first part of any ASIC design. ASIC Physical Design is the part where the design meets the physical world and therefore also the real world constrains, performance and behaviour.

The main steps of the design flow for any ASIC physical design include the following:

Design netlist – The design netlist also includes a number of different functions that the chip needs to serve as part of its design so that they can be checked off throughout the development process.

Planning and layout – All of the circuits need to be placed and laid out in a specific design. This is the main hardware component of design and simply places the basic components throughout the space given in spec.

Partitioning then takes place to make sure that all of the components are placed into logical groups for faster processing speeds and heat distribution.

Power planning can then lay out the most efficient process for the chip.

Placement – During the placement process engineers will place the individual components onto a prototype chip to see how it functions. Often optimization takes place during the prototype phases to fix the setup of the chip design.

Clock tree synthesis – During this phase the chip is heavily tested to check the placement optimization and to fix a whole host of issues before further optimization takes place.

Routing – Routing times individual circuits on the chip and recognizes the constraints. Detailing the major functions and optimizing these functions takes place during this step.

Filling – During this point the chip is filled in and included into the product for the first time.