March 11, 2020, anysilicon

DLL stands for Delay Locked Loops. A Delay Locked Loop IP core refers to a digital feedback circuit wherein there is no use of an oscillator, but instead a delay line is employed as the output is phase locked to an input. The only difference between a PLL or a Phase Locked Loop and a DLL or Delay Locked Loop is that the latter does not employ the use of an internal voltage controlled oscillator, while the former does. Or, to consider from a different perspective, a Phase Locked Loop uses a variable frequency block, whereas a Delay Locked Loop uses a variable phase block.


As such, a Delay Locked Loop can be used to change the phase of a given clock signal by producing a delay. It does not create a new clock like a Phase Locked Loop as it does not comprise of an oscillator. The change in the phase of the clock signal can be used to enhance the clock rise to data output valid, a timing that is characteristic of integrated circuits such as those found in DRAM devices.


How Do Delay Locked Loops Work?


As mentioned before, Delay Locked Loops produce a delay in the clock signal. They do so with the help of a series of delay gates arranged in the form of a delay chain which is then connected output to input. The input that is coming to the chain is connected to the clock that must be delayed along with a multiplexer that is connected to the individual stages or gates of the delay chain. Ultimately, the multiplexer is updated by a control circuit to reduce a negative delay effect which causes a negative delay in the output clock signal.


Thanks to this architecture, a circuit having a Delay Locked Loop compares the last output with the input clock, and then produces an error signal which is considered as a control signal for all of the components of the delay chain. There is no second integration to produce a new control signal through an oscillator unlike what is required in a Phase Locked Loop.


Delay Locked Loops Applications


One of the major benefits of Delay Locked Loops over Phase Locked Loops is their lower sensitivity to supply noise as well as a lower phase noise. It is also more stable and. Consequently, much more easier to design as compared to a PLL. It cannot, however, perform frequency multiplication.


There are essentially two types of Delay Locked Loops, the first one using a single input and the second one using two inputs, one each from the data and the clock. In a type 1 Delay Locked Loop, there is multiphase clock generation and the phase detector serves to compare the VCDL input and output with each other. In the type 2 Delay Locked Loop, the phase detector compared the other input with the VCDL output as only one of the two inputs is delayed and is typically used for data recovery purposes.


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