Multi-site wafer sort is a method to test silicon dies in parallel in order to reduce wafer testing cost.
The increase demand for low cost wafer sort solutions is driving companies into performing parallel wafer sort testing (Multi-site testing). Depending on the tester capabilities in terms on number of I /Os and concurrent testing support and of course the IC volume expectations, multi-site test could prove to be a good investment.
In reality, there is no 100% parallel testing in semiconductor ATE equipment’s, but still in many cases developing a multi site test solution can help reduce the test cost and speed-up the testing activities.
The semiconductor industry is referring to the following terms when it comes to multi-site testing:
Dual-site – e.g. testing 2 ICs in parallel
Quad-site- e.g. testing 4 ICs in parallel
Octal-site- e.g. testing 8 ICs in parallel
The image below shows an octal site wafer card that can test 8 dies in parallel.
