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PCIe IP Core

January 07, 2020, anysilicon

PCIe IP stands for Peripheral Component Interconnect Express IP, and it is a standard that was designed to replace the PCI, PCI X and the AGP bus standard. PCIe itself is a serial computer expansion bus standard. The purpose of introducing a new standard to replace the older versions mentioned before was to decrease the I/O pin count, decrease the physical footprint, and increase the high point for the maximum system bus throughput. Not to mention that the PCIe bus protocol also has better performance scaling for bus devices and tends to do better when it comes to error detection and reporting, giving more details thanks to the advanced error reporting or AER system.

 

The PCIe standard is not only limited within itself- in fact, it is frequently used in a number of other standards including ExpressCard and SATA Express or U.2 and M.2 for computer storage interfaces. Most commonly though, it is used as the common motherboard interface for all of the graphics cards, SSDs, Ethernet, WiFi, and hard drive connections to a given personal computer.

 

One of the prime differences between the older PCI version and the PCI Express is in that of the architecture of the bus standards. Where a conventional PCI bus uses a shared parallel bus structure, the current version in PCIe uses point to point topology in which all of the devices are connected to the host which is the root complex. This renders the new PCIe device capable of forming a full-duplex communication link between the two endpoints. It also removes any limitations that may have previously existed with older versions of PCI in regards to access and direction.

 

The size of the PCIe link between any two devices can be anywhere from one lane to up to 32 lanes. In the case that you are using a connection with multiple lanes, the packet data is usually striped across the lanes. Speaking of packets, it is important to know that communication of data across a PCIe lin is performed with the help of individual packets of data that is transferred and handled by the transaction layer of the PCIe port.

 

Another benefit that a serial bus interface has over the previously preferred parallel bus architecture is the fact that there is no timing skew. In a parallel interface, different signals take a different amount of time to get to their destination. In a serial interface, however, there is no external clock signal- only a single differential signal in each lane in one each direction, meaning there is no risk of timing skew.

 

The PCIe itself is a layered protocol and has three layers:

  • The physical layer is further divided into the electrical and logical sublayers.
  • The data link layer is responsible for sequencing and delivering transaction layer packets.
  • The transaction layer manages the flow of data.

 

Overtime, the PCIe structure and architecture has undergone revision and improvement in an effort to produce a better standard than before that has higher performance rates. Currently, we are working on developing the PCI Express 6.0 which has 64 Gbit/s data rate per lane and yields 128 GB/s in each direction when placed in a 16 lane configuration. It is currently set to release in 2021.

 

Click here for find companies providing PCIe IP Core.

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