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Standard Cells

March 24, 2019, anysilicon

Standard cell methodology is a practice employed frequently during semiconductor designing where Application Specific Integrated Circuits are designed using digital logic features. As such, one designer may focus on developing the logical function of the chip while the other can focus on the physical aspect of the semiconductor.

 

Generally, a standard cell is composed of a transistor and relevant interconnects that either provide it a logic function or a storage function. The boolean logic functions include the likes off AND, OR, XOR, XNOR, as well as inverters. This aspect of the cell is also called the logical view as it details the functional behavior of the semiconductor which can be listed down in a table or equation.

 

The development of the cell begins with the transistor netlist which lays down a schematic view of all the transistors and the interconnects between them. Designers normally run tests and simulations to determine whether or not the initial netlist performs the function they want it to perform. This is the netlist view of the cell.

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