USA
Black Forest Engineering (BFE) is a full service custom mixed-signal ASIC design house, BFE helps customers of all sizes with everything from the initial IC specification all the way to providing a functional test system. We can offer guidance for selecting optimal foundry/process to manufacture your ICs, handling of foundry and packaging interfacing and logistics, packaging and testing services, and consultation on existing projects.
BFE has completed over 300 unique designs over our 30-year history. We have a wide variety of customers in the commercial, research, scientific, government, and defense sectors. BFE has experience and patents with IC based readout of IR, visible, X-Ray detectors, camera integration, and ROICs. We offer a fully customized solution utilizing our proven IP from numerous foundries and process nodes to deliver a quality product on time.
BFE has an extensive library of proven IP that has been implemented across over 300 unique designs so we can efficiently deliver a turnkey solution to you.
Each custom ROIC needs a custom package and test set. BFE has developed specialized testing software, hardware, and methodologies to ensure an effective testing process.
Using a Time & Materials approach, BFE can offer guidance and support for any program from the planning phase, design effort, foundry selection, to the post processing.
BFE’s full custom design offers customers the ideal matching of all of their specs for their product. By making each ROIC & ASIC unique BFE is able to adapt to the challenging requirements customers may have.
Patent # 9,197,233
Advanced focal plane arrays (FPAs), such as infrared focal plane arrays (IRFPAs) utilize embedded ADCs on the read out integrated circuitry (ROIC) die. On-ROIC digital readout allows on-chip digital signal processing, increased dynamic range, and increased signal to noise ratio. On-ROIC ADC is often incorporated at one or more FPA outputs or at ROIC columns. More ADCs on the ROIC tend to provide increased digital resolution and reduced ADC power due to reduced digitization frequency.
One serious limitation of current ROIC technology is the difficulty of achieving very large charge capacity in small pixel pitch. Analog circuits do not scale well because voltages and capacitances are reduced and transistor noise increases for smaller technologies and sizes. There have been efforts to overcome these analog limitations by implementing an A/D converter in each pixel, but those we are aware of have significant problems with high noise, large power dissipation and require extremely expensive non-recurring costs for very small design rule CMOS tooling. The ADC per pixel concept (also referred to as a digital pixel sensor (DPS)) has increased difficulty of implementation in large format mega-pixel FPAs as pixel pitch is reduced (<30 μm), ADC resolution increased (>14-bits) and FPA frame rate is increased (>60 Hz).
Pixel
Array
ADC
DAC
MiM
Preamplifiers
Multiplexers
LiDAR detectors and readout
Laser drivers
Photonic counting circuits
Micro-power A/D and D/A converters
X-ray and high energy particle detectors and interface chips
Image sensors (CMOS and CCD)
Image processors
Integrated liquid crystal drivers
Bi-CMOS
BCD (Bipolar, CMOS, DMOS)
CMOS-SOS
SERDES
USB
SPI
LVDS
