CAST, Inc.

Drive embedded and IoT systems, sensor subsystems, and more with compact, low-power, 32-bit BA2x™ Family processors or small, versatile, 8051-compatible microcontrollers.

The BA2 instruction set enables great code density, significantly reducing the size of the memory devices needed for these processors. The BA2x processor family includes features, such as an ultra-low-power PipelineZero™ architecture  that help differentiate your products from everyone else’s,—while class-leading performance and area specs ensure competitive results.

Various preconfigured BA2 processors bundle features and peripherals to target deeply embedded systems through application processors running Android or Linux. All include the BeyondStudio™ IDE for quick programming, and reference designs; evaluation systems, and integration services are also available.

The 8051s from CAST offer small size, easy integration and programming, and relatively fast performance. Whether to run simple applications or to offload a main processor in larger SoCs, these soft MCS®51-compatible cores are among the most highly featured and customer-proven available anywhere.

They offer configurable CPUs and bundled peripherals, 8-bit area and power savings, easy development and test, proven reliability, and royalty-free value.

The Video and Image Compression IP family provides a range of hardware encoders and decoders for JPEG, AVC/H.264, and HEVC/H.265 video. They offer:

• Scalable performance, supporting resolutions beyond Ultra-High Definition (UHD) and/or ultra-high frame rates.

• Extremely small silicon footprints, enabling low-power and economical implementations in FPGAs and ASICs.

• Excellent video quality, even for ultra-low-latency, and/or low-bit-rate video streaming.

Each encoder and decoder satisfies particular needs for performance, power consumption, and silicon area, and offers smart trade-offs of compression degree and quality. Included are:

JPEG and Motion JPEG Encoders and Decoders, in Baseline and Extended (12-bit) variations, offering an economical yet high-quality alternative for moderate levels of video compression,

H.264/AVC Video Encoders and Decoders, supporting different profiles and featuring the lowest power consumption and smallest silicon area compared to competitive cores, and

An H.265/HEVC Decoder with versatile support for multiple profiles and video system characteristics.

CAST is one of the longest-running providers of image and video compression IP cores, with hundreds of successful customers shipping millions of media products since 1998.

The ZipAccel™ Cores enable hardware lossless data compression that is unmatched in performance, low energy consumption, flexibility, and ease of integration and use.

The ZipAccel-C Compression Core implements a lossless data compression engine that complies with the Deflate, GZIP, and ZLIB compression standards. The ZipAccel-D Decompression Core implements decompression for the same standards. A ZipAccel-C Reference Design Board offers is ready for evaluation or initial system design.

The ZipAccel-C Compression Core’s flexible architecture enables fine-tuning of its efficiency, throughput, and latency to match application requirements. Throughputs over 100 Gbps are feasible even in low-cost FPGAs; latency can be as small as a few tens of clock cycles.

The ZipAccel-D Decompression Core features fast processing, with low latency and high throughput. On average the core outputs three bytes of decompressed data per clock cycle, providing over 15Gbps in a typical 40nm technology. Designers can scale the throughput further by instantiating the core multiple times to achieve throughput rates exceeding 100Gbps. The latency is in the order of few tens of clock cycles for blocks coded with static Huffman tables, and typically less than 2,000 cycles for blocks encoded with dynamic Huffman tables.

Readily implement standard interfaces for automotive, industrial, and other applications.

The Automotive Bus IP cores from CAST feature the most production-proven CAN 2.0, CAN FD & CAN-XL controller available anywhere. It is backed with verification IP (VIP) and a ready-to-run hardware reference design board.

Automotive Bus cores also include a LIN master/slave controller, SENT/SAE J2716 transmitter/receiver controller for sensor connections.

Designed to optimize and simplify deterministic communication, our pioneering line of TSN Ethernet IP cores features high-precision timing synchronization and accurate traffic scheduling with minimum latency.

Proven and tested for their interoperability in multiple plugfests, our TSN Ethernet IP cores occupy a fraction of the silicon area of competing IP cores and require minimal software assistance.

Our line of TSN Ethernet IP cores includes Endpoints and Switches:

• A 4-port, layer-2, cut-through, low-latency TSN Ethernet Switch Core that is highly configurableand ideal for applications with demanding real-time requirements.
• A TSN Ethernet Endpoint Core suitable for star network topologies.
• A TSN Ethernet Switched / Bridged Endpoint Core suitable for daisy-chained networks.

CAST IP protocol stacks and controllers ensure easy Internet connectivity via highly efficient UDP/IP custom-hardware stack, ultra-low latency Ethernet Media Access Controllers (EMACs), RTP and MPEG Transport Stream Engines.

We present the most highly featured hardware UDP/IP stack that supports UDP/IP, ARP, DHCP, ICMP, IGMP, VLAN for 1G to 100G, and up to 32 streaming channels per direction.

CAST’s evolving MIPI IP cores family currently consists of controllers for the SPMI and I3C protocols.

CAST IPs enable easy and cost-effective serial communication functions in nearly any system. The family includes I2C-SMBUS, SPI, and a set of popular UARTs, H16450S, H16550S and H16750S, with legacy device compatibility in fully-synchronous, flexible designs.

All these IP cores conform to their respective industry standards and have been thoroughly silicon-proven in multiple customer products.

We also feature one of the broadest, most useful ranges of SPI-based, AMBA-compatible memory and data interface cores, including:

• an xSPI Flash Memory Controller
• a Simple SPI Master/Slave, and
• an SPI to AHB-Lite Bridge.

All these SPI cores support single, dual, quad and octal SPI, as well as STR and DTR transfers.

Memory controllers include Parallel NOR Flash and SPI-based flash controllers with octal or quad interfaces, with execute in place (XIP) capabilities.

You may also select from a variety of AMBA Bus compatible peripheral cores, for use in CAST subsystems, or in your own SoC. These include:

• AHB Multi-matrix Bus Infrastructure
• AXI Multi-layer Bus Infrastructure
• AXI to APB Bridge
• AHB to APB Bridge
• AHB and AXI DMA Cores
• AHB Cache Controller
• SPI to AHB-Lite Bridge
• Timers, Real Time Clock, GPIOs, serial interfaces and more.

Our Encryption primitives family enables fast, efficient encryption for a variety of applications and covers several popular security standards:

• A set of NIST-certified AES encryption and decryption cores with varying combinations of features, performance, and silicon size;
• SHA crypto engine cores, including the latest standard, SHA-3 (Keccak); and
• an MD5 Message Digest Algorithm Processor.

Smart design and easy integration features make each of these cores ready to add encryption functions to your particular system.

For more comprehensive security of complete System on Chip designs, opt for our GEON SoC Security Platform, a compact hardware root of trust solution that works with your processor of choice.

Additionally, you may select GEON Secure Processor that builds secure code execution into a 32-bit embedded processor making it suitable for security-sensitive systems such as Internet of Things devices.