CAST

Drive embedded and IoT systems, sensor subsystems, and more with compact, low-power, 32-bit BA2x™ Family processors or small, versatile, 8051-compatible microcontrollers.

The BA2 instruction set enables great code density, significantly reducing the size of the memory devices needed for these processors. The BA2x processor family includes features, such as an ultra-low-power PipelineZero™ architecture  that help differentiate your products from everyone else’s,—while class-leading performance and area specs ensure competitive results.

Various preconfigured BA2 processors bundle features and peripherals to target deeply embedded systems through application processors running Android or Linux. All include the BeyondStudio™ IDE for quick programming, and reference designs; evaluation systems, and integration services are also available.

The 8051s from CAST offer small size, easy integration and programming, and relatively fast performance. Whether to run simple applications or to offload a main processor in larger SoCs, these soft MCS®51-compatible cores are among the most highly featured and customer-proven available anywhere.

They offer configurable CPUs and bundled peripherals, 8-bit area and power savings, easy development and test, proven reliability, and royalty-free value.

The JPEG IP Family offers a set of efficient hardware encoders and decoders for Lossy compression with JPEG and its application to video using Motion JPEG.

• JPEG-E-S, JPEG-EX-S, JPEG-EX-F, JPEG-E-T: Baseline JPEG & Motion JPEG encoders.
• JPEG-D-S, JPEG-DX-S, JPEG-DX-F  : Baseline JPEG & Motion JPEG decoders.
• JPEG-XL-E: Encoder for JPEG XL, yielding higher-quality, significantly smaller image files than legacy JPEG 

Lossless encoders and decoders give you a wide range of trade-offs for function, performance, and area, all with lossless compression. Choose from:

• JPEG-LS Encoder and Decoder, for high compression efficiency,
• QOI — Quite Okay Image format — Encoder and Decoder, for small silicon footprint, and
• PNG Decoder and Encoder, balancing between silicon area and compression efficiency

The H.264/AVC Video Compression IP cores family offers a set of efficient hardware encoders and decoders for H.264 video encoding. All cores are highly optimized custom hardware engines that operate autonomously without any software assistance, and stand-out for their small silicon area and low-power consumption. The cores are suitable for live-streaming applications with stringent latency requirements. Tens of customers, have used H.264 cores from CAST in a wide range of applications. The family includes:

• H264-E-CFS: Low-power AVC/H.264 encoder with Compressed Frame Store, eliminating the need for external DRAM.
• H264-E-BPS, H264-E-BPF: AVC/H.264 Baseline Profile encoders.
• H264-E-HIS: Intra-only, 10-bit capable AVC/H.264 encoder.
• H264-D-BP: Low-power, compact AVC/H.264 Constrained Baseline Profile Decoder.

The ZipAccel™ Cores enable hardware lossless data compression that is unmatched in performance, low energy consumption, flexibility, and ease of integration and use.

The ZipAccel-C Compression Core implements a lossless data compression engine that complies with the Deflate, GZIP, and ZLIB compression standards. The ZipAccel-D Decompression Core implements decompression for the same standards. A ZipAccel-C Reference Design Board offers is ready for evaluation or initial system design.

The ZipAccel-C Compression Core’s flexible architecture enables fine-tuning of its efficiency, throughput, and latency to match application requirements. Throughputs over 100 Gbps are feasible even in low-cost FPGAs; latency can be as small as a few tens of clock cycles.

The ZipAccel-D Decompression Core features fast processing, with low latency and high throughput. On average the core outputs three bytes of decompressed data per clock cycle, providing over 15Gbps in a typical 40nm technology. Designers can scale the throughput further bydd instantiating the core multiple times to achieve throughput rates exceeding 100Gbps. The latency is in the order of few tens of clock cycles for blocks coded with static Huffman tables, and typically less than 2,000 cycles for blocks encoded with dynamic Huffman tables.

The LZ4SNP-C high-speed hardware compression core and LZ4SNP-D decompression core support LZ4 and Snappy format.

IP Cores –  Interfaces:

Automotive cores are proven and reliable and include:

• An industry-leading CAN Controller, which supports CAN CC, CAN-FD, TTCAN, and CAN XL, and can optionally be augmented by a CANsec Accelerator 
• A LIN Bus Master/Slave Controller, compatible with LIN specification 2.0, 2.1, and 2.2A, and backward compatible with LIN specification 1.3
• A Microsecond Channel Controller supporting MSC and MSC-Plus protocols for high-speed serial links between automotive SoCs and external power or sensor devices
• A SENT/SAE J2716 Receiver, compact, configurable receiver that implements the SAE J2716 SENT protocol, enabling reliable, high-resolution digital communication
• A SENT/SAE J2716 Transmitter, compact, fully synchronous transmitter that implements the SAE J2716 SENT protocol, enabling low-cost, high-resolution digital communication
• A Low-Latency Ethernet MAC suitable for automotive ethernet, including the 10BASE-T1S and 100BASE-T1 standards
• A multiport TSN Ethernet Switch  supporting cut-through, ultra-low latency operation
• A TSN Ethernet Endpoint (10G) suitable for star network topologies 
• A TSN Ethernet Switched Endpoint  suitable for daisy-chained networks 
• A SafeSPI v2.0 controller supporting the master, slave, and monitor roles and optionally acting as an autonomous SafeSPI-to-AXI bridge

IP Stacks easily build Internet connectivity with this family of IP protocol stacks and controllers.

• TCP/IP Hardware Stacks offer complete, all-hardware, low-latency TCP/IP stacks, implementing: TCP, IP, ARP, DHCP, ICMP and optionally DHCP, UDP, IGMP, VLAN-  TCPIP-1G/10G
• UDP/IP Hardware Stacks offer highly-featured, all-hardware UDP/IP stacks, supporting:
  UDP, IP, ARP, and optionally DHCP, ICMP, IGMP, VLAN- UDPIP-1G, UDPIP-10G/25G, UDPIP-40G/50G, UDPIP-100G, UDPIP-400G
• Ethernet Media Access Controllers (eMACs) for 10/100/1000 Mbps with Scatter-Gather DMA and optional PTP- LLEMAC-1G, EMAC-1G
• MACsec Protocol Engine hardware protocol engine protecting data confidentiality and integrity as per the IEEE 802.1AE standard- MAC-SEC-1G, MAC-SEC-10G 
• MPEG Transport Stream Engine encapsulates audio, video, and metadata streams in a single MPEG Transport Stream- MTS-E

Audio – Simplify audio integration for ASIC and FPGA systems with these high-quality audio interface IP cores.

• AC’97 Audio Controller (AC97-CTRL)— A compact, configurable core supporting AC’97 Rev. 2.3
• Audio Sample Rate Converter (ASRC)— Combining synchronous and asynchronous conversion modes
• I2S/TDM Multichannel Audio Transceiver (I2S-TDM)— A full-duplex, multi-channel audio transceiver supporting I2S and TDM modes
• PDM Receiver/PDM-to-PCM Converter (PDM2PCM) – A configurable audio interface core that converts a mono or stereo Pulse Density Modulation (PDM) stream into standard Pulse Code Modulation (PCM) format. 

MIPI IP cores family currently consists of:

• SPMI-CTRL: MIPI System Power Management Interface (MIPI-SPMI) interface core, which can act either as a controller or as a target
• I3C-T: MIPI Improved Inter-Integrated Circuit (I3C) Basic target core
• I3C-SC: MIPI Improved Inter-Integrated Circuit (I3C) Basic secondary controller core

CAST IPs enable easy and cost-effective serial communication functions in nearly any system. The family includes I2C-SMBUS, SPI, and a set of popular UARTs, H16450S, H16550S and H16750S, with legacy device compatibility in fully-synchronous, flexible designs.

All these IP cores conform to their respective industry standards and have been thoroughly silicon-proven in multiple customer products.

We also feature one of the broadest, most useful ranges of SPI-based, AMBA-compatible memory and data interface cores, including:

• an xSPI Flash Memory Controller
• a Simple SPI Master/Slave, and
• an SPI to AHB-Lite Bridge.

All these SPI cores support single, dual, quad and octal SPI, as well as STR and DTR transfers.

Memory controllers include Parallel NOR Flash and SPI-based flash controllers with octal or quad interfaces, with execute in place (XIP) capabilities.

You may also select from a variety of AMBA Bus compatible peripheral cores, for use in CAST subsystems, or in your own SoC. These include:

• AHB Multi-matrix Bus Infrastructure
• AXI Multi-layer Bus Infrastructure
• AXI to APB Bridge
• AHB to APB Bridge
• AHB and AXI DMA Cores
• AHB Cache Controller
• SPI to AHB-Lite Bridge
• Timers, Real Time Clock, GPIOs, serial interfaces and more.

IP Cores –  Peripherals

CAST offers IP cores that conform to their respective industry standards and have been thoroughly silicon-proven in multiple customer products to provide the critical IP functions required for your design.

DMA Controllers cores are optimized for diverse data movement needs in modern SoC designs. These cores support memory-to-memory, streaming, multichannel, and scatter-gather operations across standard AMBA and Wishbone interfaces, delivering efficient, low-latency data transfers with minimal CPU intervention.

DMA-CTRL — A memory-to-memory, highly configurable, compact DMA controller that transfers data over AHB, AXI, or Wishbone busses

AXI4-DMA — A streaming DMA controller, transferring data between an AXI4 memory-mapped interface and a peripheral with AXI4-Stream interfaces

MC-SDMA — A multichannel, streaming DMA controller transferring data between an AXI4 memory-mapped and up to 16 AXI4-Stream interfaces per direction.

AXI4-SGDMA — A scatter-gather, streaming DMA controller, transferring data between an AXI4 Memory-Mapped interface and an AXI4-Stream interface.

Memory Controllers support different types of memories, including :

• xSPI-MC  — A universal serial memory controller supporting NOR Flash, NAND Flash, and PSRAM Memories. Compatible to xSPI, Hyperbus, Xccela and most vendor-specific SPI protocols.  Allows a system to easily detect and access an attached flash device, or directly boot from it. 
• CACHE-CTRL — A flexible cache memory controller providing a 32-bit slave AHB-lite processor interface and a 32-bit master AHB-lite interface to the memory subsystem.
• SRAM-CTRL —  An SRAM Controller translating AHB, or AXI4, or APB bus reads and writes into reads and writes with the signaling and timing of a standard 32-bit synchronous SRAM. 
• ECC-SRAM —  A core that adds Single-Error Correction / Dual Error Detection (SECDEC) to any SRAM, without altering its access latency 

Serial Communications cores make it easy and cost-effective to integrate these functions in nearly any sort of system. The family includes:

• I2CSPI-CTRL a compact and versatile serial interface controller supporting both SPI and I2C protocols;
• SPI-MS — a controller for a single-, dual-, quad-, or octal-lane Serial Peripheral Interface (SPI) bus, which can operate either as a master or as a slave;
• SPI2AHB — a SPI-to-AHB bridge allowing an external SPI master accessing the local AHB bus. 
• I2C-SMBUS — a serial interface controller for the Inter-Integrated Circuit (I2C) bus and the System Management Bus (SMBus); and
• H16450S, H16550S and H16750S — a set of popular UARTs, with legacy device compatibility in fully-synchronous, flexible designs; and
• HSDLC — a controller for the High-Level Data Link Control (HDLC) and the Synchronous Data Link Control (SDLC) protocols. 

IP Subsystems pre-integrate AMBA bus-fabric and peripheral subsystems and provide the quickest path from your creative product idea to a competitive working system. These register transfer level (RTL) Subsystems are designed with the total system in mind. They combine: an AMBA® bus infrastructure , typical peripheral, interface, and memory controller IP cores, and all essential drivers and software.

Microcontroller Peripherals complement CAST’s serial interfaces, memory controllers, bus fabric IP cores, and pre-integrated subsystems. Cores in this family include:

• I2S-TDM — A highly configurable I2S/TDM multichannel audio transceiver
• SCR — A versatile Smart Card Reader Controller compatible with the latest EMV specifications 
• MM2ST  — An AHB/AXI4-Lite to AXI4-Stream Bridge
• RTC-APB — A Real-Time Clock with an accuracy of 1/10 of a second 
• TIMER-APB — A generic Timer/Counter
• WDT-APB — A Watchdog Timer 
• GPIO — General-Purpose IO Controller 
• PWM — Pulse Wdith Modulator

Symmetric Crypto cores are efficient engines which include:

• A set of NIST-validatedAdvanced Encryption Standard (AES) cryptographic engines with varying combinations of features, performance, and silicon size
• ASCON,the NIST-validated lightweight encryption standard
• SNOW-V, a successor of SNOW 3G stream cipher for 5G and beyond security and performance demands
• SM4, a compact and high-performance implementation of the Chinese national standard block cipher

Cryptographic Hash IP cores provide fast and efficient hardware engines that implement various Secure Hash Algorithm (SHA) and Message Digest (MD) standards for your system. This family includes:

• SHA-256, a NIST-validated engine that implements the widely-used SHA-256 cryptographic hash function
• SHA-384/512, a custom-hardware accelerator for the SHA-384 and SHA-512 cryptographic hash functions
• SHA-3, a NIST-validated SHA-3 (Keccak) engine
• MD5 Message Digest Algorithm Processor

Post-Quantum Cryptography (PQC) engines implement acceleration for the latest NIST-standardized PQC standards, enabling efficient, future-proof security against quantum threats while fitting seamlessly into modern system architectures. This family includes:

• KiviPQC-KEM, implementing Module Lattice-based Key Encapsulation Mechanism (ML-KEM)
• KiviPQC-DSA, implementing Module Lattice-based Digital Signature Algorithm (ML-DSA)
• KiviPQC-Box, low-area, performance-efficient, and multi-mode implementation for both ML-KEM and ML-DSA

SoC Security protects against hacking and data loss is a critical challenge for systems of every scale and application area — from embedded devices to complex System-on-Chip (SoC) designs. CAST provides three approaches to IP cores that help implement security measures in your system:

• The GEON Secure Processor builds secure code execution into a 32-bit processor suitable for embedded systems and Internet-of-Things (IoT) devices
• The GEON-SoC Security Platform offers an efficient, hardware Root-of-Trust (RoT) solution that works with your choice of processor
• The GEON Secure Boot, an area-efficient, processor-agnostic, hardware engine that protects SoC designs from booting with malicious or otherwise insecure code