ChipGlobe

• RTL Design: VHDL, Verilog, SystemVerilog, SystemC
• Gate Level Verification
• Analog Design
• Synthesis
• STA (Static Timing Analysis)
• DFT
• Test simulation
• Pattern ATPG
• Formal Verification
• Floor Planning
• Place&Route
• Power Analysis, UPF
• Linting, CDC Checks
• Physical Verification (DRC/LVS)
• CTS
• IR Drop Analysis
• Low Power and Multi Voltage Designs
• Prototyping
• Broad tool experience with Cadence, Mentor
• and Synopsys environments

• Constrained random coverage driven verification
• Mixed signal metric driven verification
• UPF/CPF power aware verification
• Verification planning and verification management
• support of SystemVerilog, UVM, Verilog, VHDL, SystemC, e environments
• setup of testbench architecture
• Languages: e, System C, C++, SystemVerilog, RNM (Real number modelling), Verilog, Verilog-AMS, VHDL
• Constraint random coverage driven verification
• Mixed signal metric driven verification
• Portable Stimulus
• Secure Designs and verification based on ISO26262
• UVM/OVM

• Cadence: JasperGold ®, Incisive ® Enterprise Simulator (HAL), Conformal ® Constraint Designer, Genus™ Synthesis (RTL Compiler), First Encounter®, Tempus™, Genus™ (RTL Compiler), Modus™ test, Conformal®, Incisive® Enterprise Simulator

• Mentor Graphics: DFT Advisor, BSD Architect, MBISTArchitect™, LBISTArchitect™, Tessent® Testkompress®, Fastscan™, Modelsim®
• Synopsys: SpyGlass®, SpyGlass® CDC, Design Compiler®, PrimeTime®, MSSTA (mixed signal), DFT Compiler/DFTMAX™, TetraMAX®, VCS®, TetraMAX® LBIST,
• DFT and ATPG
• Synthesis
• STA (Toplevel, hier. Design, Macrolevel, mixed signal)
• Constraining (General, DDR, SerDes Interface)
• Formal Verification
• VHDL and Verilog Design Expertise
• RTL Validation and Linting
• Low Power and Multi Voltage Designs

• Ansys/Apache: ANSYS® Redhawk™
• Cadence: Conformal® Equivalence Checker, Conformal® Low Power, First Encounter®, Innovus™ (Encounter®), Quantus™ QRC, Physical Verification System (PVS), Voltus™
• Mentor Graphics: Calibre®,
• Synopsys: Formality®, IC Compiler™ (ICC, ICC2), Star-RCXT™, ICV / Hercules™, Primerail
• Physical Layout
• Layout
• Layout Verification
• IR Drop Analysis
• Low Power and Multi Voltage Designs
• Functional Verification
• Cadence: Incisive® XL, vManager™, mixed signal extention to Incisive® Enterprise Simulator, Low Power extentions
• Mentor Graphics: Questa® verification platform products, Modelsim®
• Synopsys: VCS® Verification Platform products

• Secure hardware based security designs for LAN/WLAN and IoT, cloud access.
• Connection to Amazon cloud and other safe german clouds
• Analog/Digital Design
• Hardware Development
• PCB Layout, Prototyping and Testing
• Firmware Development
• Software Design and Development
• Embedded Software Development
• Software Application Development
• Hardware Board Design and Development
• Bring-up drivers and Diagnostics
• Porting of custom OS and Core Applications
• Hardware Board Redesign and Improvement
• BSP creation from scratch for different processor arcitectures and Real Time OS, Linux mainline kernel configuration and adjustment, versatile peripherales driver development support

Software for Desktops and Servers, Digital Signal Processing and algorithm development, interfaces of a large number of different devices with USB, RS232, RS485, TCP/IP…