Device Engineering Incorporated

• ECL Logic
• High Capacitance Drive IC’s
• High Voltages (>40 to 1650V)
• Thermal Control
• Pierce Oscillator
• Imaging
• Very Low Phase Noise Frequency Synthesizer  (-160dBc/Hz > 5 kHz)
• On-Chip Lightning Protected Inputs (Transients up to 600v) DO160 Level 3
• Backplane Transceiver Logic (6 ns delay)
• Transient Voltage Protection (100V/ 100μs Transient Suppression)
• RMS Conversion
• Low Power (nA, sub 1V)
• Lighting Bus Mapper
• Programmable Gain
• Relay Driver/ Control
• LED Dimmer

Device Engineering uses Industry Standard design tools based upon Personal Computer Platforms. Our expertise and tools include, but are not limited to:

• Cadence RF Design Suite
• SIMetrix (SPICE/Schematic
• Viewdraw/ ModelSim
• Tanner Design Suite (Layout/DRC/LVS/SPR)
• Leonardo-Spectrum (Schematic/CircuitSim/Layout/DRC/LVS/LPE)
• SILVACO Design Suite
• PSpice
• IC Editors ICED (Layout Editor)

DEI designers have decades of experience with Military, Avionics, Commercial, and Industrial Integrated Circuit Design and Production Flows. DEI has teamed with experienced design groups to provide RF ASIC Design, Radio Frequency Integrated Circuits, and Wireless Integrated Circuits solutions to our customers.

Our design team’s expertise lies in the following areas:

• Read channels for mass storage
• PLLs from 200 MHz to 12 GHZ
• Low Noise Frequency Synthesizers
• SERDES circuits from 2.5 Gbps to 10 Gbps
• RF radio blocks from 900 MHz to 9 GHz
• LNA, Mixers, Up/Down Converters, Filters, PAs, AGC, ADC
• UWB: OFDM and DSS
• Extensive VCO experience: LC, Rings
• 10 Gbps optical comms including TIA, LDD and Limiting Amps

• Cadence Front End Schematic capture, Spectre, Spectre RF, Verilog, AHDL, and Mixed Mode simulation
• Cadence Back EndLayout, DivaDRC, DivaLS, Assura
• NASSDA HSIM event driven simulator
• Matlab Communications package
• DSP blockset
• Simulink
• Protel
• Labview

• 20V Bipolar Analog Array. Can design to 40V or above with Cascoding:  Large NPN Transistors (200mA)
• Single Level Metal Customized:  PNP Transistors βeta = 40 to 90, ft = 15 MHz
• 32-35 wks to Ceramic Prototypes from Completion of Layout:  Turn-key Design & Layout Services Available
• Standard or Custom Packages:  NRE Typically $80k to $150k for a five-wafer minimum run
• NPN Transistors:  Typical βeta = 200, ft = 800 MHz

700 Series 4uM Bipolar Analog Array – Data Archive

700 Series Brochure

700 Series Data Sheet

700 Series Design Manual