TURKIYE
ElectraIC develops ASIC / FPGA, microchip and embedded software/systems, electronic circuit design and verification projects for many companies thanks to its expert team.
In addition to engineering services, ElectraIC develops IP cores and embedded system products. Not only does it offer services, but it also offers opportunities to differentiate with niche products and solutions in its area of expertise.
ElectraIC is a Doulos Certified Training Partner, a world-leading training services company providing the highest quality training services all around the world.
More than 200 different trainings, particularly AMD Xilinx, VHDL, SystemVerilog, UVM, SystemC, ARM, Embedded Linux, Embedded Software, and Deep Learning, are carried out in fully equipped unique training rooms. In this way, it also aims to improve the skills and professional competencies of the teams coming from the customers.
Advanced Verification in IC design means using the latest verification methodologies like UVM, UVVM, OSVVM. Our team has experience using those methodologies in FPGA design of aerospace and defence projects and ASIC design verification projects.
We will generate verification metrics and report them back to you so that you will have proof of the quality of the verification environment. The confidence level of your design will gradually increase as we present the code coverage metrics, such as statements, branches, FSMs, conditions, and expressions in your design code. Functional coverage metrics will also be provided to see how much of your design requirements are covered.
WHAT CAN WE DO FOR YOU?
ELECTRA IC takes the ownership of:
Our core competence is Digital IC Design. Hence, we have extensive experience working in ASIC/FPGA or PCB design projects. Just provide us with the system specification, and we can design and verify the ASIC/FPGA and/or PCB. If needed, we can do the mechanical design and production and deliver you the final product.
We can design an embedded system as a part of a complete device system that includes hardware, such as electrical and mechanical components. Unlike the general-purpose computer, the embedded system is engineered to manage a wide range of processing tasks. Because an embedded system is engineered to perform specific tasks, we may optimise size, cost, power consumption, reliability, and performance. Embedded systems require different software design philosophies and disciplines where real-time performance, responsiveness, robustness, resiliency, cost, power, and memory budgets are the main parameters.
WHAT CAN WE DO FOR YOU?
For EMBEDDED SYSTEMS:
For EMBEDDED SOFTWARE DESIGN:
DO-254
Having worked on avionic projects, we had the experience of using DO-254 guidance for electronics hardware development. We know DO-254 objectives and help our customers achieve a successful DO-254 certification. We can help you deploy DO-254 objectives in your electronics hardware development projects.
ISO 26262
We can implement and help you with ISO 26262 standard compliance for automotive electronics hardware development. We can help you on your journey to a successful ISO 26262 certification.
EN 50129
During your EN 50129 process, we can help you generate the related documentation to implement and generate process assurance related to the standard. We can also act as an Independent Verification Team whenever required.
TURNKEY SOLUTIONS
We take the whole ownership of;
COMPLIANCE SOLUTIONS
We work with you to deploy;
CONSULTANCY SOLUTIONS
We support you by providing;
A professional Engineer Training Programme from engineers expert in their fields!
EIC Academy Engineer Training Programme is a probation period programme for recruits. A group of 6 to 10 new engineers goes through an 8-week intensive programme, which includes training on different topics, hands-on project practices, presentation of what has been studied during the training and detailed evaluation feedback given by expert engineers in their fields. Certified Training Instructors deliver the training, projects are mentored by expert engineers and the assessments are conducted by at least three experts. To complete the programme, candidates must successfully pass the overall assessments.
EIC Academy is a professional Engineer Training Program in “Digital Design and Advanced Verification Techniques”.
As part of the EIC Academy, young engineers undergo an 8-week intensive program that includes “training in the field of Digital Design & VHDL and System Verilog & UVM”, “applied projects”, and a detailed “assessment report” prepared by expert engineers in their fields. This allows young engineers to start their business life more equipped.
MIL-STD-1553 IP is an IP Core which implements the MIL-STD-1553B standard and provides a single or multi-functional interface between the host processor and the MIL-STD-1553 bus transceiver.
MIL-STD-1553 IP can function as a Bus Controller (BC), two separate Remote Terminal (RT) and a Bus Monitor (BM) simultaneously.
COMMON SPECS
64K bytes internal static RAM with RAM Error Detection/Correction option
16-bit time tag counters and clock sources for all terminals
64-Word Interrupt Log Buffer
Built-in and optional self-test for protocol logic, digital signal paths and internal RAM
Programmable 50/100 MHz Clock Frequency
DO-254 Compliant certification package
BUS CONTROLLER SPECS
Fully programmable Bus Controller
Bus Controller has 32-bit time count options
Programmable Status Set
Message Format Check
16 Condition Code for all opcode
64-Word General Purpose Queue for external BC Host
Programmable Inter-Message Gap Time (resolution 1us)
Programmable Message Timeout
REMOTE TERMINAL SPECS
Two independent Terminal Core
Programmable different buffer modes for all Subaddress
Subaddress-based illegal command declaration
Optional temporary buffer
BUS MONITOR SPECS
Basic Bus Monitor (BBM) records commands and data separately, with 16-bit or 48-bit time tagging
Optional support function for IRIG-106 data packets, including full packet headers and trailers
Bus Monitor has 32-bit and 48-bit time count options Message Filter Table
ARINC664 End System IP is an IP Core that implements ARINC664 part 7 and provides interface between aircraft LRUs and ARINC664 network. As an implementation of End System, IP sends the user’s messages of different sizes and different time constraints to their destination with a predictable delay. Since the IP core uses the Ethernet interface when connecting to the network, it takes full advantage of the physical layer functions that Ethernet offers. Thanks to the AXI4 interface provided with IP Core, adaptation can be made between any protocol and ARINC664.
FUNCTIONAL SPECS
Supports 32 VLs
Adjustable BAG values (1ms to 128ms, 125 us to 32 ms)
Supports 64 Byte as Lmin and 1471 Byte as Lmax
Redundancy enable/disable capability
Integrity Checking enable/disable capability
Outputs error statistic
ARINC664 Switch IP implements ARINC664 part 7 and provides switching functionality within the ARINC664 network. As an implementation of ARINC664 Switch, IP switches/routes messages of different sizes and time constraints to their destination with a predictable delay. Two level of priority can be applied to the VLs during device configuration. Thus, the switch can arrange the data queues according to these priorities. Thanks to the AXI4 interface provided with IP Core, error statistics can be fetched to a desired logic and data injection to the network can be accomplished if desired.
FUNCTIONAL SPECS
Supports 128 VLs
Adjustable BAG values
Supports 64 Byte as Lmin and 1471 Byte as Lmax
Adjustable message priority (two classes)
Multicasting ability
Outputs error statistic
INTERFACE SPECS
AXI4 interface for host communication
Two ARINC664 Ethernet interfaces
End System configuration through AXI4 interface
100 Mbps/1000 Mbps Ethernet
ARINC 429 IP Core implements ARINC 429 standard. IP Core contains Rx and Tx processing blocks, Controller Block, Internal Memory and External Memory Interfaces. A429 IP communicates with CPU (Central Processing Unit) and external memory through AXI interface.
IP Core uses the AXI interface as an internal local bus. AXI interface is a 32-bit data bus which has 32-bit addressing and 32-bit read and write channels. IP supports 32 receive channel number and 16 transmit channel number.
The IP is designed to be compatible with DO-254. ARINC 429 IP is field approved.
SPECS
Supports ARINC 429 Specification
Configurable up to 32 Rx and 16 Tx Channels
Supports 12.5 kbit/s and 100kbit/s data rates
Contains 32-bit local data bus
Contains Individual and Circular buffer area which have 1024 word depth for each channel
Supports single and periodic data transfer
Filter mechanism based on SDI, ESSM, Label of ARINC 429 data
Occurring of filter process in FPGA
Communication with CPU and external memory
Field Approved
DO-254 compliant
DELIVERABLES
Encrypted VHDL source code
ARINC 429 IP Core User Guide
Optional DO-254 Certification Data Package is available
LICENSING
The following licensing models are available:
Encrypted Netlist
Encrypted RTL
Encrypted RTL with DO-254 Certification Data Package
SUPPORT
With the initial licensing, customers will receive the following services for the first year:
Half-day “IP Core First Time User Training”
Support during SOI meeting preparations is available with DO-254 Certification Data Package
IP Core update
Optimize your 5G NR O-RAN Split 7.2X design with EIC cutting-edge PRACH Design and Verification Suite. This comprehensive suite includes an end-to-end MATLAB model, RTL implementation of the MATLAB model, and a robust verification environment for bit-exact simulation and testing. Ensure seamless integration and accelerate your development process with EIC 5G NR O-RAN compatible solution.
SPECIFICATIONS
Frequency Range: FR1
Duplex Mode: TDD
Numerology: 1
Maximum Frequency Multiplexing: 8
Supported Input Sampling Rates: 30,72; 61, 44; 122,8 MSPS
PRACH Format Support: All formats
PRACH Configuration Index Support: All Indexes
PRACH Length Support: 139, 839
OVERVIEW
Comprehensive Support: All PRACH formats and configuration indexes described in 3GPP 38.211 are fully supported.
Versatile Sequences: Length-139 and length-839 sequences are included.
Frequency Multiplexing: Capable of decoding up to 8 frequencies multiplexed PRACHs.
Flexible Subcarrier Spacing: Supports both 15 and 30 kHz PRACH subcarrier spacing for short formats.
PRACH MATLAB MODEL
O-RAN Compatibility: Input stimuli generation and C-Plane Section Type: 3 message generation for each PRACH occasion.
Configurable Input: Option to constrain the number of frames and resource blocks.
Advanced Signal Processing: Three signal processing chains implemented:
Precision PDP Calculation: Performed at the end of each processing chain.
Configurable Bit Reduction: Allows adjustment of bit reduction amounts at each module’s output.
Data Dumping: Possible after each module.
PRACH RTL DESIGN
Direct Implementation: RTL implementation of the MATLAB model’s fixed-point signal processing chain.
Extensive Frequency Resource Extraction: Capable of extracting up to 8 PRACH frequency resources.
Detailed Information: Provides CC ID, Section ID, and RU Port ID information.
Flexible Decimation: Supports 1 to 96x decimation.
Robust FFT Support: Handles 256 to 8192 point FFT after decimation.
Industry Standard Interface: Utilizes AXI4-Stream interface.
PRACH RTL TEST ENVIRONMENT
AXI4-Stream IQ Data Driver: Takes input stimuli generated by the MATLAB model and feeds them into the RTL signal processing chain.
C-Plane Section Type: 3 Message Driver: Processes C-Plane messages generated by the MATLAB model and feeds them into the RTL signal processing chain.
MATLAB Model-Based Reference: The PRACH Design and Verification Suite uses the MATLAB model as a reference, allowing for the comparison of outputs from sub-blocks with MATLAB references. This feature simplifies the debugging process and enhances verification accuracy.
Extensive Test Scenario Support: Provides RTL verification scenarios for all PRACH formats and indexes.
