GS Microelectronics

FAB & Bump

• MPW
• Tape Out
• Engineering Wafers & Corner lots
• Wafer Manufacturing
• Bumping

Package Design

• Package selection
• Substrate Design
• Thermal Simulation
• SIPI Simulation
• Package Qualification

Test Development

• Tester Platform selection
• DFT(design for test)
• Device test plan
• ATE Characterization
• Software development
• Hardware development
• Test Correlation
• Yield Improvement
• Test Time Reduction
• Mass Production
• RMA test support

Product Engineering

• Monitor production yields
• Monitor PCM & WAT data
• Lot hold criteria for Production
• Support FA & Reliability
• OSAT Qualification
• Yield improvement
• DPPM Monitor

Reliability

• ESD/LU & HTOL board design
• Qualification test plan
• Procedure for reliability testing
• Qualification testing
• Qual Reporting

Product Sustaining

• Yield Improvement
• Test Optimization
• Lower DPPM
• Lower cost

Failure Analysis

-Root cause field failures

-FA reporting

-FA testing

• C-SAM analysis
• X-Ray analysis
• Demounting, Rework, Redress
• TDR Analysis
• Laser De-cap
• Liquid Crystal analysis
• Emission Microscopy analysis
• OBRICH analysis
• TEM & EDX analysis
• De-processing & SEM analysis

– Package & Die cross section analysis

Characterization

-Device validation

-Device & System level characterization

-Characterization reporting

-Support Design/Product/Test engineers

-Target yield setting

Target DPPM setting

• Chip Specification
• Partitioning Chip
• Functional Verification
• RTL Synthesis
• DFT (Design for Test)
• Floor Planning
• CTS (Clock Tree synthesis)
• Place & Route
• Final Verification
• GDS II