GS Microelectronics


  • A Value-Added Semiconductor Solutions Provider, with emphasis on meeting the technical requirements at lower cost, high quality and time to market
  • Silicon Valley’s best in class experts in innovation, IC design and manufacturing with over 140 engineers globally with offices in US, Taiwan and Oman
  • Single stop shop for end to end semiconductor solution for design services from RTL to Layout, Tape out, Wafers, Assembly, Test, Reliability, CIP
  • Team with over 100 tape-outs combined knowledge and expertise in delivering end-to-end products
  • Dedicated TSMC OIP Partner as official VCA Candidate. Fully support Global Foundries, Samsung and UMC foundries.
  • Strong partnerships in semiconductor ecosystem with access to resources, capacity and preferred pricing.
  • Semiconductor industry veteran board guiding company plan and roadmap


Manufacturing Services

FAB & Bump

  • MPW
  • Tape Out
  • Engineering Wafers & Corner lots
  • Wafer Manufacturing
  • Bumping


Package Design

  • Package selection
  • Substrate Design
  • Thermal Simulation
  • SIPI Simulation
  • Package Qualification


Test Development

  • Tester Platform selection
  • DFT(design for test)
  • Device test plan
  • ATE Characterization
  • Software development
  • Hardware development
  • Test Correlation
  • Yield Improvement
  • Test Time Reduction
  • Mass Production
  • RMA test support


Product Engineering

  • Monitor production yields
  • Monitor PCM & WAT data
  • Lot hold criteria for Production
  • Support FA & Reliability
  • OSAT Qualification
  • Yield improvement
  • DPPM Monitor



  • ESD/LU & HTOL board design
  • Qualification test plan
  • Procedure for reliability testing
  • Qualification testing
  • Qual Reporting


Product Sustaining

  • Yield Improvement
  • Test Optimization
  • Lower DPPM
  • Lower cost

Failure Analysis & Characterization

Failure Analysis

-Root cause field failures

-FA reporting

-FA testing

  • C-SAM analysis
  • X-Ray analysis
  • Demounting, Rework, Redress
  • TDR Analysis
  • Laser De-cap
  • Liquid Crystal analysis
  • Emission Microscopy analysis
  • OBRICH analysis
  • TEM & EDX analysis
  • De-processing & SEM analysis

– Package & Die cross section analysis



-Device validation

-Device & System level characterization

-Characterization reporting

-Support Design/Product/Test engineers

-Target yield setting

Target DPPM setting


Design Services

  • Chip Specification
  • Partitioning Chip
  • Functional Verification
  • RTL Synthesis
  • DFT (Design for Test)
  • Floor Planning
  • CTS (Clock Tree synthesis)
  • Place & Route
  • Final Verification
  • GDS II