India
InCore is a leading provider of PPA-optimised RISC-V processor IP for a wide variety of applications, from deep embedded and low power, to high performance compute and domain-specific accelerators.
InCore also automates RISC-V SoC design, using highly customizable RISC-V cores and pre-integrated 3rd party IPs from our partners. InCore’s “SoC Generator” platform converts your SoC specifications (YAML config file) to SoC RTL which is correct-by-construction and fully synthesizable – all this in under 15 minutes!
InCore’s Core-hub Generator, an automated platform, allows users to configure core components. It produces a synthesizable Core-hub instance, along with fabric, uncore, and accelerators. Leveraging RISCV-CONFIG technology, users have fine-grain control over architectural choices, translated to RTL by InCore’s Core-hub Generators.
A Core-hub is a compute-subsystem consisting of customizable RISC-V cores, versatile interconnect fabrics, standard RISC-V UnCore components, and performance-enhancing accelerators.
Robust Tech Stack
We use BSV, Python, eUVM to achieve rapid design space exploration & prototyping capabilities within the Core-hubs.
Massive Configurability
Baseline cores-hubs can further be configured & finetuned at the ISA & uarch levels to meet PPA targets.
Holistic Collaterals
Automated generation of Documentation, Physical Design collaterals, FPGA collaterals, ASIC collaterals and Software Toolchain, ensuring rapid design and integration into the SoC.
High Quality IP
Core-hubs feature a highly configurable verification environment utilizing novel tech such as eUVM and ASM generators to create comprehensive test cases for maximum IP coverage.
Fast-track RISC-V SoC design, using highly customizable RISC-V cores and pre-integrated 3rd party IPs from our partners. InCore’s “SoC Generator” platform converts your SoC specifications (YAML config file) to SoC RTL which is correct-by-construction and fully synthesizable – all this in under 15 minutes!
RISC-V Core-hub Generator
Custom Core + Fabric + Uncore + Docs in 15 minutes! (truly leverage the promise of RISC-V in silicon)
NOC generator
By maintaining a robust portfolio of interconnect fabrics, we allow users to iterate at rapid speed on NOC architecture
Accelerator & IP generator
Standardised minimum resistance wrappers + Domain specific axls (in-house) + ability to integrate any 3rd party IP seamlessly
Verification generator
Automates test generation and reduces manual intervention significantly
Software generator
Automates BSP creation for selected OS and builds SW stack components like IDE, SDKs, compilers etc.
InCore Azurite is an extremely compact, RISC-V 2-stage pipelined micro-processor. Built on Incore’s proprietary deep-customization stack for microarchitectural exploration, Azurite delivers industry-beating performance in an exceptionally small silicon footprint. A 32-bit processor at the cost of a traditional 8-bit price point.
Azurite is comparable to ARM Cortex M-0, M-0+, M-23, M-3 and M-4 cores.
The Azurite core comes bundled as a compute subsystem, with integrated AMBA protocol interconnects (supports AXI4, AHB, APB) and uncore components (debug, trace, interrupt controllers etc)
Features
– 32-bit RISC-V core
– 2-stage pipeline
– Available in many versions:
– 32/16 general purpose registers
– Multiplier
– RISC-V privilege mode support:
– Optional FPU (single precision)
– Optional unified tightly coupled memories (TCM)
– Optional 8 or 16 PMP regions
– Optional L1 data and instruction caches
– Optional L2 cache
– Optional Internal interrupt controller
– Optional Standard RISC-V CLINT
– Optional NMI
– Optional Trace
– RISC-V Debug module
– 2/4 pin JTAG
– 2-8 breakpoints/watchpoints
Benefits
– Configurability
– Time to Market
– PPA
Applications:
InCore Calcite is a powerful and Linux-capable core designed for the embedded and industrial segments, targeting applications from POS terminals to IP cameras.
Calcite is comparable with ARM Cortex A-35.
Features:
