Mirafra

RTL Design

• RTL development from Specification
• Module and Sub-System level RTL design
• SOC design integration

Design Verification

• IP/Sub-system
• SOC
• Processor
• VIP
• Formal
• GLS

FPGA & Emulation

• Design
• Validation
• Prototyping
• Emulation

Post Silicon Validation

• Emulation
• IP/Sub-System, SOC Functional Validation
• AMS Bench Characterization

Synthesis & STA

• Synthesis for Blocks and SOCs
• Constraints development
• Power, congestion and physical aware
• Timing Budgeting and Closure
• Timing Closure with X-talk effects, OCVs and ECO’s
• MMMC based timing optimization

DFT

• DFT at IP and SOC level
• ATPG, MBIST, PBIST, IDDQ and DC Para
• Test time reduction, pattern generation, probe and tester use

Physical Design & Automation

• Blocks & SOCs level PnR
• Low Power Implementation
• PD CAD Support
• Scripting & Automation support
• Methodology & flow development

Physical Verification

• DRC and LVS
• Antenna
• Density

Mixed Signal Design/Layout

• Power Management
• Clock System
• Data Converters
• Interfaces, SerDes, DDR and USB

RF Layout

• RF frontend Rx/Tx
• LNA, Bias & Mixer

Memory Development

• Design, Layout & Characterization
• Custom and Compiler Memories
• Dual / Single port memories

Std Cell/IO Library

• Design & Layout
• Characterization & Modelling