Mirafra

Mirafra’s verification team has proven expertise on taking complete ownership of verification of a design from scratch – whether that is an IP/SOC/subsystem – and taking it to verification closure by performing the following activities:

• Understanding the design specification document and creating the test plan
• Creating the complete verification environment using industry standard methodologies like UVM/OVM/VMM
• Executing the test plan by using an intelligent mix of constraint random, directed and random test cases
• Gate level simulations
• Verification closure through corner case verification, coverage closure and regression closure

The AMS verification team at Mirafra has the skillsets required to execute on:

• Analog/mixed-signal block simulations
• Modelling of analog and mixed signal blocks using Verilog-AMS
• Creating digital mixed signal test benches
• Comprehensive AMS full chip verification of mixed signal ASICs.

Mirafra Verification team also has hands on expertise with System-C Verification

Mirafra’s Physical Design, Implementation & Verification Service offerings are comprised of having expertise in following domains

• Synthesis/Formal equivalence/UPF flow/CLP checks support

• Extensive support on DFT insertion and Simulations

• Hierarchical/Flat level chip implementation

• Core Hardening or block Build development

• Die Size optimization and related scripting and automation support

• Physical Verification/DFM support for Hard Macros and full chip level

• Signoff timing closure with X-talk effects, OCVs and ECO’s implementation

• Low Power Implementation for Static/Dynamic reductions

• EDA/CAD flow & methodology support

Highlights: 

• Process Nodes from 3nm to 28nm and higher
• EDA tools from Synopsys, Cadence, Siemens (Mentor) & Ansys
• Domain experience in Graphics, Wireless, Networking, Server/Client, Automotive SoCs & various IP Implementation
• Low Power, Mixed Signal & Higher performance designs

• Scope: Digital logic and microarchitecture, SOC integration,
  Linting, CDC, Formal, UPF
• Verticals: Networking, Mobile, Processor, Memory/Storage
• Protocols: PCIe, USB, Ethernet, SATA, DDR, LPDDR, Camera

• DFT Implementation – Scan Insertion and Stitching, MBIST, JTAG, LBIST, Compression, DRC
• ATPG – Pattern Generation and Simulation/Debug
• Post Silicon Debug
• Modus, DFT Compiler, DFTMAX , Tetramax, Tessent, Test-Kompress, Spyglass, VCS, NCSim

• Analog, IO and Mixed Signal IP development
• Power Management (Ref/BGR/LDO/Buck/Boost/drivers)
• Clock System (Osc/PLL/DLL), Data Converters (ADC/DAC)
• Interfaces, USB, SerDes and DDR
• Full-chip layout executions
• Circuit design in Power Management, IO, SerDes and DDR modules

• Scope: Design, Validation, Prototyping, Emulation
• Verticals: Telecom, Networking, Wireless, IoT, Memory/Storage
• Protocols: PCIe, USB, Ethernet, SATA, DDR, LPDDR, Camera
• Languages: Verilog, VHDL, System Verilog, HLS
• Emulation Platforms: HAPS, Zebu, Palladium, Custom Board