USA
MosChip is a semiconductor and system design company with a focus on Turnkey ASICs (RTL to Silicon), Design Services, Mixed-Signal IP, Embedded Systems, System Engineering and targeted IoT solutions catering to the Computing, Industrial, Consumer Electronics, Automotive, Medical, Networking & Telecommunications, and Mobile industries. Our unique processes are specifically designed to comply with the high performance and long-term reliability needs of our customers. We are your partner throughout the product development cycle, designing & building comprehensive and best-in-class solutions in time to achieve your business & operational goals eventually, keeping you at the forefront of the ever-changing competitive market.
We provide SoC/ASIC/IP RTL Design Services.
Our team of design engineers have in-depth experience in various aspects of the RTL design flow on chips used in different verticals. MosChip with more than 20+ years of experience on designs going up to 100 million+ gates, emerged as a leader in the industry as the leading RTL design services provider for complex designs.
We provide SoC/ASIC/IP Verification Services.
Verification Audits
Verification
Modeling Capabilities
Low Power Verification & CPF/UPF Flows
Experience in :
SERDES
Short reach custom SERDES
Transceivers (Bluetooth/WIFI,USB, Ethernet, Networking)
Data converters
RF
Power Management ICs
IOs including ESDs
Memories
Display port
Image sensor etc
Foundry (process nodes):
TSMC (7ff, 6ff, 12ff, 16ff, 22nm, 28nm)
Samsung (ss4, ss5, ss7, ss10, ss14, 28nmFDSOI)
GF (7lp, 12lp, 14lp, 22nm FDSOI, 55nm)
Experience in:
Foundry
Process Nodes
500nm all the way down to 16nm/14nm/10nm/7nm
MosChip’s PHY technology provides high-speed serial data interface (SerDes) IP which helps in developing low-cost, low-power SoC for various networking applications. We offer customization of SerDes to multiple foundries/nodes, emerging standards and porting to customer’s own technology.
Enhanced simplex High-Speed STP macro with data transfer capabilities of up-to 6.25/12.5Gbps. It includes a Standard ARM HS-STP simplex interface. In addition, on the same footprint using our technology, it can include a standard JTAG interface.
Enhanced multi-lane PCIe Gen2 macro that is backward compatible to previous generations with data transfer capabilities up to 5 Gbps. It includes a PCIe standard multi-lane interface. PHY is suitable for both Root Complex and End Point applications within a PCI Express system. The PHY provides a comprehensive feature set, a well-defined architecture that allows designers extensive flexibility for various applications, and a roadmap to future products. Additionally, the PHY provides support for a number of PCI Express addendums and extensions including the Mobile Graphics Low Power addendum and the Wireless Form Factor extension.
XAUI PHY supports up to 3.2G backplane applications. The benefit of these highly integrated PHY solution include differentiated performance, simplified interoperability and extensive built-in testability.
CEI-SR PHY supports up to 6.4G backplane applications. This comprehensive PHY family covers a wide range of standards from 1.06 Gbps to 6.4 Gbps with the smallest footprints in the industry.
The SATA1/2 PHY is suitable for both Host and Device applications within a Serial ATA system. The SATA PHY operates to the Serial ATA specification using either a 10-bit or 20-bit interface to a Serial ATA Link Layer where the 8b10b encoding and decoding of the data is done. Recovered data is provided using SATA compliant D-word alignment. The SATA PHY provides a comprehensive feature set, a well-defined architecture that allows designers extensive flexibility for various applications, and a roadmap to future products.
