MosChip Technologies


MosChip is a semiconductor and system design company with a focus on Turnkey ASICs (RTL to Silicon), Design Services, Mixed-Signal IP, Embedded Systems, System Engineering and targeted IoT solutions catering to the Computing, Industrial, Consumer Electronics, Automotive, Medical, Networking & Telecommunications, and Mobile industries. Our unique processes are specifically designed to comply with the high performance and long-term reliability needs of our customers. We are your partner throughout the product development cycle, designing & building comprehensive and best-in-class solutions in time to achieve your business & operational goals eventually, keeping you at the forefront of the ever-changing competitive market.


RTL Design

We provide SoC/ASIC/IP RTL Design Services.

Our team of design engineers have in-depth experience in various aspects of the RTL design flow on chips used in different verticals. MosChip  with more than 20+ years of experience on designs going up to 100 million+ gates, emerged as a leader  in the industry as the leading RTL design services provider for complex designs.


We provide SoC/ASIC/IP Verification Services.

Verification Audits

  •  Verification Audits at all level to find and address the verification Gaps.
  • Suggestion of methodologies and working closely with the team.


  • Levels
    • Block/Unit
    • Cluster/Sub system level
    • Full Chip/SoC level
  • Methodologies
    • Dynamic & Static Verification
    • Proficient usage of advanced concepts like eRM/OVM/UVM(1.1) methodologies.
    • System Verilog, C and Assertion based verification.
    • Metric driver verification concepts.

Modeling Capabilities

  • Test bench development
  • Development of BFMs, Monitors and checkers
  • Functional and code coverage analysis
  • Verification IP development


Low Power Verification & CPF/UPF Flows

Analog Layout

Experience in :



Short reach custom SERDES

Transceivers (Bluetooth/WIFI,USB, Ethernet, Networking)

Data  converters


Power Management ICs

IOs including ESDs


Display port

Image sensor etc


Foundry (process nodes):


TSMC (7ff, 6ff, 12ff, 16ff, 22nm, 28nm)

Samsung (ss4, ss5, ss7, ss10, ss14, 28nmFDSOI)

GF (7lp, 12lp, 14lp, 22nm FDSOI, 55nm)

Physical Design

Experience in:

  • Constraints Preparation and Validation
  • Logic Synthesis and Physical Synthesis
  • Physical Design (IO ring, Floor planning, PG Planning, Place, Optimization for Timing and Power, Clock Tree Synthesis, Routing, Post Route Optimization) on multi-million gate designs
  • Low Power Expertise – Clock Gating, Multi-Vt, Voltage Islands, Power Gating
  • EM & IR drop analysis, SI Closure
  • Timing Closure and Static Timing Analysis
  • Physical Verification (DRC/ERC/LVS)


  • TSMC, UMC, Chartered/Global Foundry, IBM, Tower Jazz, Samsung

Process Nodes

500nm all the way down to 16nm/14nm/10nm/7nm

System Engineering

  • Turn-key Product Solutions with System, FPGA & Software Development
  • Reference Designs for PoC, Si Bring-up, Functional Validation & Characterization
  • Formfactor Designs for Custom or COTS Enclosures
  • Platform Bring-up & Validation.
  • Complex & High-Speed System Design
  • System Architecture
  • Schematic Design
  • PCB Layout Design
  • SI/ PI/ Thermal Analysis
  • Mechanical Enclosure Design
  • Prototyping & Volume Manufacturing through eco system partners
  • Design Control with Process Workflow for Libraries & Design Data Base Management / Maintenance
  • Product improvements and feature additions, Design updates along with Revision Control
  • Design Documentation & Ownership

Embedded Software/Firmware

  • Board Support Package (BSP) & OS Porting
  • Linux, VxWorks, Android
  • Device Drivers Development
  • Bare Metal and OS
  • Multimedia, Connectivity & Memories
  • 3rd Party IP Integration and Test App Development
  • System Integration & Software Testing
  • GUI Development for Embedded Systems
  • Sustenance and Derivative Product Development
  • Customization, Maintenance & Support

IP Cores

Custom SerDes

MosChip’s PHY technology provides high-speed serial data interface (SerDes) IP which helps in developing low-cost, low-power SoC for various networking applications. We offer customization of SerDes to multiple foundries/nodes, emerging standards and porting to customer’s own technology.

ARM HSSTP PHY with Link Layer

Enhanced simplex High-Speed STP macro with data transfer capabilities of up-to 6.25/12.5Gbps. It includes a Standard ARM HS-STP simplex interface. In addition, on the same footprint using our technology, it can include a standard JTAG interface.


Enhanced multi-lane PCIe Gen2 macro that is backward compatible to previous generations with data transfer capabilities up to 5 Gbps. It includes a PCIe standard multi-lane interface. PHY is suitable for both Root Complex and End Point applications within a PCI Express system. The PHY provides a comprehensive feature set, a well-defined architecture that allows designers extensive flexibility for various applications, and a roadmap to future products. Additionally, the PHY provides support for a number of PCI Express addendums and extensions including the Mobile Graphics Low Power addendum and the Wireless Form Factor extension.


XAUI PHY supports up to 3.2G backplane applications. The benefit of these highly integrated PHY solution include differentiated performance, simplified interoperability and extensive built-in testability.


CEI-SR PHY supports up to 6.4G backplane applications. This comprehensive PHY family covers a wide range of standards from 1.06 Gbps to 6.4 Gbps with the smallest footprints in the industry.


The SATA1/2 PHY is suitable for both Host and Device applications within a Serial ATA system. The SATA PHY operates to the Serial ATA specification using either a 10-bit or 20-bit interface to a Serial ATA Link Layer where the 8b10b encoding and decoding of the data is done. Recovered data is provided using SATA compliant D-word alignment. The SATA PHY provides a comprehensive feature set, a well-defined architecture that allows designers extensive flexibility for various applications, and a roadmap to future products.