Pacific MicroCHIP

• SystemVerilog, Verilog, VHDL coding
• Synthesis
• Verification
• Place and route
• Scan chain insertion
• DFT

• Compiling Specifications
• Verilog A Level Design
• Behavioral Simulation
• Circuit Level Design
• Simulation
• Physical/Layout Design
• Post Layout Optimization
• Chip Assembly
• Tape out Logistics

• ASIC/IC/RFIC Design
• Chip Fabrication Logistics
• Package Development
• Chip Packaging
• PCB Development for Testing/Evaluation
• Testing/Characterization (In-house Lab)
• System PCB Development
• Delivery of Chips, Parts and Board Level Solutions

• Feasibility Study
• Design Environment Setup
• Preparation of Specifications
• Analog IC Design
• Mixed Signal Design
• Digital Frontend and Backend Design
• Physical Design
• PCB Design

• Schematic Capture
• BOM (Bill of Materials) Compiling
• Layout and Routing
• Signal Integrity Analysis
• Documentation and Support

• FPGA Prototyping
• Hardware and Software Integration
• ASIC/SOC Bring Up
• Testing
• Failure Analysis
• Yield Improvement

Large portfolio of analog IP in different technologies from TSMC, GF, XFAB, Tower.

Several ADC/DAC IP in TSMC Technologies

• JESD204B+
• SPI
• I2C