Ramtera

LVR is Ramtera’s physical verification engine. One tool runs design rule checking (DRC), layout versus schematic (LVS) and electrical rule checking (ERC) on a shared geometry core and design database, so one rule deck and one results flow cover the whole verification job.

• DRC: full foundry DRC decks, including width, spacing, enclosure, density, antenna, double-patterning decomposition, latch-up and ESD rules. The die is tiled and processed in parallel across CPU cores.
• LVS: device and connectivity extraction from layout, SPICE/CDL netlist input and graph-based layout-versus-schematic comparison.
• ERC: floating gates and nets, unconnected MOS terminals, isolated devices and bulk-polarity checks, run on the same extracted database with no second extraction.
• Layout XOR: compare two versions of a GDSII layout.

LVR reads GDSII layouts hierarchically and writes results in the standard ASCII results-database (RDB) format, so existing result viewers and scripts can read them. For DRC, it is invoked the same way as the industry’s established tools. It runs on 64-bit Linux, is multithreaded and is driven by its own command language.

Physical verification is only as good as its rule deck. LVR is built to run the foundry’s own rules, not a hand-translated approximation.

LRF (Layout Rule Format) is Ramtera’s native rule language. It is designed for one-to-one correspondence with established foundry rule decks: statement for statement and line for line, with Boolean operators and standard terms unchanged. A foundry deck converts to LRF mechanically, so every rule, condition and derived layer is preserved, and engineers who know the original deck can read the LRF version immediately.

LVR runs production foundry decks on FD-SOI and FinFET technologies. On GlobalFoundries 22FDX, 12LP and 12LP+, LVR’s DRC results have been compared marker by marker with golden reference results across the foundry test suites, and they match on every compared rule, with documented waivers.

Finding violations is half the job; fixing them quickly is the other half. LVR includes the tools engineers need to close verification:

• Layout editor: a Qt-based editor for viewing layouts and stepping through DRC and LVS results.
• Custom-layout integration: a SKILL integration package that overlays LVR markers directly in custom-layout environments.
• Waiver database: approved exceptions are stored with a fingerprint of rule, layer, cell and location, so waivers stay attached to their violations from run to run.
• Licensing: node-locked and floating licences, served by LVR’s own licence daemon with a seat-status tool.
• Distributed runs: a foreman process spreads a run across a compute farm through LSF; it works on first designs and is being tuned for speed.

LVR-PEX, a companion parasitic extraction tool with SPEF and DSPF output, is in development.

PRE is Ramtera’s place-and-route engine. It reads a Verilog netlist with LEF, Liberty and SDC files and carries the design through placement, clock tree synthesis and routing to DEF and GDSII.

• Placement: analytical, ePlace-style Nesterov global placement, followed by legalization and detailed placement.
• Clock and timing: clock tree synthesis, Liberty/SDC timing analysis with multi-mode, multi-corner support, and sizing and buffering.
• Routing: global routing, track assignment and a multithreaded detailed router, with PRE’s own design-rule and connectivity checkers inside the routing loop.
• Proven on open designs: on the SKY130 benchmark designs, from a 570-cell GCD block to a 13,569-cell RISC-V core, PRE connects 100% of nets with zero opens. PRE has also run designs on GF180MCU and IHP SG13G2.

PRE is driven by Tcl commands in a familiar industry style, runs headless or with a Qt GUI, and works inside OpenROAD-flow-scripts. Its GDSII output goes straight to LVR for verification, giving a complete netlist-to-GDSII flow from one vendor.

Chip design is moving toward AI agents that run, check and fix design steps on their own. Ramtera is building LVR for that shift.

Ramtera has built an MCP server for LVR, now in pre-release testing. It exposes LVR’s checks as tools that any Model Context Protocol (MCP)-capable agent can call: the agent submits a layout and rule deck, LVR runs the check, and structured results come back for the agent to act on.

• Runs on your infrastructure: the LVR container runs on your own machine or cloud account, so layouts and foundry decks never leave your environment.
• Pay per run: licensing per verification run instead of annual seats, a natural fit for bursty, agent-driven workloads.

Contact Ramtera to discuss early access.

Ramtera offers hands-on training courses taught by its founder, Dr. Sameer Pawanekar, who holds a PhD in VLSI placement and partitioning and was a postdoctoral researcher with the OpenROAD team at the University of California.

• Place & Route with PRE: the physical design flow from gate-level netlist to routed layout.
• DRC/LVS with LVR: physical verification with foundry rule decks, from running checks to debugging results.

Courses use PRE and LVR as the lab tools, so participants work hands-on with a complete flow. Training is available for engineering teams, new graduates and universities. Contact us for course details and pricing.