Rydev
USA
Time-to-market is king in the ASIC world. And we know how difficult it is to find ASIC design houses capable of delivering on-time, with the expected quality, and for the right price. That’s why we have gathered a team of specialists in the latest Digital and Analog IC industry standards, methods, and tools, ready to take care of your design critical needs. From product specification, architecture design, RTL design and verification, up to physical signoff, we’ve got you covered.
Services
RTL Design
Our RTL team has solid experience in:
- SystemVerilog, VHDL
- Standard and Complex IP Block Design and Development
- SoC and Sub-system Integration
- Clock and reset design, Clock gating, Low-power design, UPF
- Lint, CDC, Automated property checks, Low-power checks
- HSIO Protocols (PCIe)
- AMBA protocols (AXI/AHB/APB)
- High speed SERDES interfacing
- Memory interfaces (DDRx/LPDDRx)
- Low-speed peripheral interfaces (I2C, SPI, UART, MDIO, I2S)
Design Verification
Our verification team is fully conversant in:
- IP and SOC-level Verification using C/C++, SV-UVM methodologies (UVM 1.1, 1.2)
- CPU (RISC-V, Tensilica) processed based on verification
- Test plan development and implementation, using modern project management techniques (Jira) to achieve Functional and Code Coverage goals
- Power-aware verification
- Gate-level simulations and regression management
- SV assertions
Physical Design
Our engineers can support any custom SoC development with advanced backend techniques supporting each customer technology, all the way down to commercial 7 nm. Our back end design expertise includes:
- Place and route
- Floorplanning
- Clock tree synthesis
- Timing closure
- Power analysis
- Low power techniques and multiple power domain control under the UPF standard
- LVS
- Physical verification and GDSII generation
Analog Design
Our analog engineers have strong experience in analog and mixed signal IC design from 350 nm and 180 nm HV planar nodes down to 65 nm and SOI technologies. Some of our past designs include: Bandgap references, Sigma-Delta modulators, ADCs, LDOs, OpAmps, UVLs, high order continuous filters, HV current sources, etc.
Our team’s analog expertise using the major EDA tools providers includes:
- Specification writing and feasibility analysis
- Circuit design and simulation
- Analog and custom digital layout design
- Physical verification of the design (DRC, LVS, ERC, DFM)
- Layout parasitic extraction and post-layout simulation
- Verilog A and Verilog AMS model development
IP Cores
RISC-V Ultra-Low Power Core
Silicon-tested ultra-low-power RISC-V based microcontroller on a 0.18um and 65nm CMOS commercial processes.
- Silicon-tested ultra low power (48.31 pJ/cycle @1MHz per core on 0.18um commercial process.
- Ultra-Compact RISC-V 32RVI compatible microcontroller: dual and single core IP solutions (less than 32k gates per core)
- Include SPI, Bootstrap, UART and SRAM memory controllers.
- Full instruction-set implementation (32RVI 32-bit base integer) with custom special GPIO instructions
- IP is capable of replacing 8 and 16-bit microcontroller solutions while being flexible and expandable to 32-bits, maintaining complete compatibility to RISC-V open-source toolchains.
Configurable Clock-Gated 32-bit Bus Manager
This generic IP bus generator facilitates power management and integration of other IP blocks to a RISC-V core, memory controllers, SPI blocks and standard APB/AHB protocols.
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