Rydev

Our RTL team has solid experience in:

• SystemVerilog, VHDL
• Standard and Complex IP Block Design and Development
• SoC and Sub-system Integration

• Clock and reset design, Clock gating, Low-power design, UPF
• Lint, CDC, Automated property checks, Low-power checks
• HSIO Protocols (PCIe)
• AMBA protocols (AXI/AHB/APB)
• High speed SERDES interfacing
• Memory interfaces (DDRx/LPDDRx)
• Low-speed peripheral interfaces (I2C, SPI, UART, MDIO, I2S)

Our verification team is fully conversant in:

• IP and SOC-level Verification using C/C++, SV-UVM methodologies (UVM 1.1, 1.2)
• CPU (RISC-V, Tensilica) processed based on verification
• Test plan development and implementation, using modern project management techniques (Jira) to achieve Functional and Code Coverage goals
• Power-aware verification
• Gate-level simulations and regression management
• SV assertions

Our engineers can support any custom SoC development with advanced backend techniques supporting each customer technology, all the way down to commercial 7 nm. Our back end design expertise includes:

• Place and route
• Floorplanning
• Clock tree synthesis
• Timing closure
• Power analysis
• Low power techniques and multiple power domain control under the UPF standard
• LVS
• Physical verification and GDSII generation

Our analog engineers have strong experience in analog and mixed signal IC design from 350 nm and 180 nm HV planar nodes down to 65 nm and SOI technologies. Some of our past designs include: Bandgap references, Sigma-Delta modulators, ADCs, LDOs, OpAmps, UVLs, high order continuous filters, HV current sources, etc.

Our team’s analog expertise using the major EDA tools providers includes:

• Specification writing and feasibility analysis
• Circuit design and simulation
• Analog and custom digital layout design
• Physical verification of the design (DRC, LVS, ERC, DFM)
• Layout parasitic extraction and post-layout simulation
• Verilog A and Verilog AMS model development