Secure-IC

France

With presence and customers across 5 continents, Secure-IC is the rising leader and the only global provider of end-to-end cybersecurity solutions for embedded systems and connected objects.

 

Driven by a unique approach called PESC (Protect, Evaluate, Service & Certify), Secure-IC positions itself as a partner to support its clients throughout and beyond the IC design process. Relying on innovation and research activities, Secure-IC provides Silicon-proven and cutting-edge protection technologies, integrated Secure Elements and security evaluation platforms to reach compliance with the highest level of certification for different markets (such as automotive, AIoT, defense, payments & transactions, memory & storage, server & cloud).

Services

Post silicon security evaluation tool - Analyzr

ANALYZR supports common embedded systems technologies, including: FPGA, ASIC or End-Device. It allows the security assessment of any type of implementation.

Using the Analyzr, running a security evaluation is a set of simple steps, which allow going end-to-end from the hardware setup and the acquisition up to the security evaluation report. This security evaluation can be passive physical attacks such as Side Channel Attack and/or active physical attack such as Fault Injection Attack.

 

The platform comes with several equipment and materials necessary to conduct a full evaluation covering the highest security levels as specified by standards.

The Use-Cases are practical user-guides and tutorials that provide a turnkey template to support and guide the ANALYZR user through an evaluation methodology: from the acquisition to evaluation. The ANALYZR provides a rich and full Use-Cases solution ranging from basic analyses on unprotected crypto designs to more sophisticated analyses on full target with crypto and non-crypto modules. The solution comes with structured projects including the target, analysis sources and ready templates for report generations.

 

ANALYZR provides a complete and rich user command line interface (CLI) that allows the evaluator to script an end-to-end process based on a console. The end-to-end scripting process includes sequentially: SCA analysis setting and SCA analysis run.

In addition to licensing the platform software, Secure-IC also provides tools to perform active attacks. Plug in your algorithms, attack, analyze at the bit level, reinforce.

 

Key features

End-to-end analysis: from Acquisition to Analysis and Evaluation Report generation

Supported analysis:

  • Side-Channel Analysis (SPA, DPA, CPA, LRA, etc.)
  • Fault Injection Analysis (based on clock, power, EM, laser)

Delivered with all platform (SCA, EM Fault Injection, Laser Fault Injection, Power and Clock Glitch station)

Delivered with advanced triggering solution (Smart-Trigger Advanced)

 

Benefits

Ensure the security evaluation of any kind of devices

Multiple targets: FPGA, ASIC, Microcontroller, End-Device, Test-chip

Compatible with large scale of Oscilloscope

2 interfaces: GUI and CLI

Windows and Linux supported

Delivered with use-cases (reference cases)

Software security evaluation tool - Catalyzr

The CATALYZR is a software tool that aims at assessing the security of a Software (SW) implementation. The CATALYZR allows the security assessment of any type of software implementation based on C code.

 

In fact, the CATALYZR provides an end-to-end workflow that starts by an input software and ends by a security report generation. This workflow implements the Diagnose-Verify-Cure approach that helps investigate and point-out vulnerabilities in the source code in order for the developer to correct through an iterative process until the code is clean.

 

The Use-Cases are practical user-guides and tutorials that provide a turnkey template to support and guide the CATALYZR user through an evaluation methodology: from the SW coding practices to evaluation.

 

The solution comes with structured projects including the target design, analysis sources and ready templates for report generations. The goal behind is to help the user improve his skills in terms of both aspects: SW coding for security and gathering expertise for SW security evaluation.

 

Key features

  • End-to-end analysis: from Acquisition to Analysis and Evaluation Report generation
  • Supported analysis:
    • Side-Channel Analysis (SPA, DPA, CPA, LRA, etc.)
    • Fault Injection Analysis (based on clock, power, EM, laser)
    • Cache attack
  • Target level: source code level & Run-time level
  • Vulnerability mapping in the code to support designer to solve the vulnerability

 

Benefits

  • 2 interfaces: GUI (web-based) and CLI
  • Windows and Linux supported
  • Delivered with use-cases (reference cases)
  • Best analysis condition

Pre-silicon security evaluation tool - Virtualyzr

Through the VIRTUALYZR tool we present an innovative way to verify the security of the design at the pre-Silicon level. Such an early stage verification of the security can be seen as new Electronic Design Automation (EDA) tool that allows to add a new layer of verification to the lifecycle of an embedded implementation before being packaged into a chip.

The VIRTUALYZR is a software tool that aims at assessing the hardware security layer of an embedded system at the pre-silicon stage.

 

The VIRTUALYZR is used at the digital design level and provides an end-to-end workflow that starts by a design input and ends by a report generation. This tool allows detecting potential vulnerabilities that might exist in the design.

The VIRTUALYZR exploits simulation activity results in order to build an equivalent of power consumption traces and then perform physical analysis. It allows the detection and localization of leakage nodes in the design. The leakage detected can be due to many errors in the design like a miss-integration or a weak countermeasure. It can be also behind a bad synthesis of the design.

The VIRTUALYZR is mapped with the HDL simulator to run simulation of the design.

 

Key features

  • End-to-end analysis: from Acquisition to Analysis and Evaluation Report generation
  • Supported analysis:
    • Side-Channel Analysis (SPA, DPA, CPA, LRA, etc.)
    • Fault Injection Analysis (based on clock, power, EM, laser)
    • Focused Ion Beam and probing analysis
  • Vulnerability mapping in the code to support designer to solve the vulnerability – Leakage finder and leakage detection metrics

 

Benefits

  • HW Target: RTL, Nestlist, Layout
  • 2 interfaces: GUI (web-based) and CLI
  • Windows and Linux supported
  • Delivered with use-cases (reference cases)
  • Best analysis condition
  • Compliant with multiple HDL simulators & emulators

Support to Certification

A step by step guidance in the certification process from the roots to certification (CC, FIPS 140, ISO, CSPN).

 

All our technological security solutions come with a set of services and support. Starting with the customer request and discussions about the security requirements, we first deliver the related IPs specifications and then the IP cores themselves. Before the chip manufacturing stage, we provide a support to integration and after the chip manufacturing step we can also provide a support to certification.

 

Secure-IC supports its clients during the certification process by providing help to answer laboratories’ questions and providing the evaluation laboratories with all the required details on its technologies.

 

Thanks to its analysis tools (Virtualyzr and Analyzr), Secure-IC can also deliver security robustness pre-evaluation reports.

Evaluation as a Service

Compliance to any standard certification level.

 

Pre silicon Post Silicon Software evaluation by Laboryzr.

 

Software code or real device evaluated (White Box or Black Box against Reverse Engineering) and Pre Quotation & tailored Design for Security Recommendations.

 

SoC Evaluation

 

To avoid extra costs and delayed time to market, validate your design prior to the certification process. Thanks to our home-made evaluation tools, Secure-IC can provide on-chip characterization of the level of resistance against attacks of our products after integration in clients’ designs.

 

Embedded Security Evaluation as a Service

 

Before the design, during the design, and after the design, Secure-IC supplies evaluation as a service for governments, design houses, HW/SW applications developers and end-user technology manufacturers.

 

The end goal is to help companies be ready and succeed at any level of standard certification.

 

Within the “evaluation as a service” solution, you can:

 

  • Check compliance of target evaluation to standard certification levels
  • Test the target evaluation against advanced attacks
  • Review code design and structure
  • Review security design & integration level
  • Select algorithmic and specification level
  • Select appropriate countermeasure
  • Pre-silicon evaluation analysis
  • Software analysis
  • White box/Black box evaluation

IP Cores

Securyzr iSE

As part of Secure-IC’s iSSP (integrated Security Service Platform), Secure-IC is able to provide integrated Secure Elements (iSE) that can act as trust anchors that protect the security assets of a device. An iSE – also referred as HSM or Security Subsystem or Root of Trust – is an IP block that can be embedded into every device to ensure security services such as key management, lifecycle management, Secure Boot & updates

 

Secure-IC’s Securyzr provides the core security services required to build a security architecture for a wide variety of devices and connected objects: mobile, payment device, smart card, ECU, Set-Top-Box, and HSM.

 

Key features

  • Services:
    • Secure Boot
    • Secure Firmware update
    • Life-cycle management
    • Secure Key and certificate Management (storage, generation, revocation, provisioning)
    • Cryptographic service (encryption, decryption, Digital signature computation & verification, hash computation)
    • Secure Connectivity support (TLS, IPSec)
  • Tunable embedded cryptography (AES, RSA, ECC, Whirlpool, SM2, SM3, SM4, etc.)
  • Certification-ready (FIPS-140-3, OSCCA, Common Criteria)
  • Compliant with highest security level
  • Tunability by market requirement (automotive, IoT, Smart Grid, STB, AI chip, etc.)
  • Compliant with standardized API (PKCS #11)
  • 32-bit RISC-V secure processor – Secure Software Isolation

 

Benefits

  • Easy to integrate
    – Tunable solution
    – Fully digital
    – AMBA interface
    – Strong technical support (HW and SW)

Digital TRNG

Random number generation is a keystone in security.

 

Secure-IC offers both True Random Number Generator (TRNG) resilient to harmonic injection for statistically independent sets of bits generation and Deterministic Random Bit Generator (DRBG) for high bitrates requirements. These random generators are compliant with all required statistical tests suites.

 

Key features

  • Fully Digital and based on standard cells
  • Compliant with: AIS-31 (PTG.1 to PTG.3), NIST FIPS 140-3, NIST SP 800-90, GM/T 0005-2015
  • Robust against process, temperature and voltage variations
  • Post-silicon fine tuning to ensure high-level functional safety
  • Fully hardware AIS-31 embedded tests: “Mono-bit”, “Poker”, “Run” and “Long run” tests
  • Fully adaptable according to customer’s needs in terms of throughput, frequency and area
  • Easy to integrate
  • Compliant with any FPGA and ASIC technology

 

Benefits

  • Tunable solution
  • Fully digital
  • AMBA interface
  • Strong technical support

Digital PUF

The storage of a key in a non-volatile memory represents a risk to retrieve the key and a deterministic generation makes the key vulnerable to attacks based on observation.

 

PUF Security IP is a secret key generation system based on Physically Unclonable Functions. The secret key is extracted by the PUF from the silicon by using its unique intrinsic properties caused by tiny manufacturing discrepancies: technological dispersions are amplified into digital signals (bits of information). The key generated is not readable but extracted using a group of helper-data. This distinctive feature allows a real protection against the reverse-engineering techniques compared to traditional methods that store the key in non-volatile memory.

 

Key features

  • Proven reliability regarding voltage, temperature and aging with error probability much lower than 10-9.
    • Lifetime > 25 years
    • Temperature range: -40°C to 125°C
  • Fully Digital and based on standard cells
  • Transferable to any Design Kit
  • Delivered as soft IP
  • Flexible reliability and time to answer
  • Free RAM PUF
  • Small amount of helper data
  • Protected against side-channel observation during key extraction using randomization
  • AMBA interface
  • Easy to integrate

 

Benefits

Master Key generation for example for to ensure firmware’s confidentiality

 

Addressed Threats

  • Firmware tampering
  • Invasive probing
  • Side-channel analysis
  • Fault injection analysis
  • Invasive hardware modifications (FIB)
  • Used for root of trust establishment

Software Crypto Library

SW implementation of cryptographic engines.

 

Necessary algorithms for these applications and optional support or joint development:

  • Secure Boot
  • AES
  • HMAC or RSA or ECC
  • Full Disk Encryption
  • AES-XTS
  • AES
  • HMAC

 

Countermeasures

  • Protection against timing attacks, including cache attacks
  • Protection against Row Hammer attacks

 

Optionally

  • Protection against embedded system attacks
  • Hardware TRNG, for key generation, IV generation

 

Key features

  • Against attacks on software
  • Certification ready

 

Cryptographic Library:

  • AES Software Implementation
  • RSA Software Implementation
  • ECC Software Implementation
  • Hash Software Implementation
  • MAC Software Implementation

 

Digital Sensor – Smart Monitor powered by AI for Cybersecurity

The Digital Sensor is designed to detect various threats belonging to the family of Fault Injection Attacks (FIA):

  • Input clock frequency (clock glitches, Overclocking): reduction of the clock period to provoke a critical path violation.
  • Input voltage (power glitches, underfeeding): reduction of supply voltage to increase the propagation delay of combinational logic.
  • Temperature (heating): modification of the temperature to increase the propagation delay.
  • Radiations (laser spot, light spot, Electromagnetic): provoke bit set or reset in registers by irradiation.

 

Digital Sensor converts all monitored stresses into a timing stress which is then measured. When a threat is detected, it provides the system with a measurement of the threat’s level and it raises the hardware alarm.

To instate a security module, as a security headquarter, handling all security events and statuses, Secure-IC developed Smart Monitor. It has the ability to centralize all information concerning the health of the device. In addition, it can be interfaced with customer’s sensors (analog or digital) to increase the sources of information and specific data.

 

Key features

  • Detects global and local fault injections as laser, EMFI, clock or temperature
  • Real-time hardware alarm
  • Also provides a stress level status vector
  • No calibration after design
  • Fully Digital and based on standard cells
  • Transferable to any Design Kit

 

Benefits (Digital Sensor)

  • Easy to integrate
  • Lightweight
  • AMBA interface
  • Strong technical support

Active Shield

Active Shield technology is designed to deter intrusive attacks by placing a mesh over the sensitive parts of the circuit and actively monitoring the mesh’s integrity. This counter-measure protects the circuit’s features such as metal routing and transistors that are beneath the mesh from undetected access or modification through the front-side, including:

  • Wire micro-probing to read or force an equipotential with Focused Ion Beam
  • Wire cutting (e.g. alarms, entropy source disconnection from a TRNG…)
  • Wire re-routing
  • Burnt fuses opening
  • ROM Altering
  • Scanning imaging attacks (PICA, LVP/LVI)

 

The mesh is actively monitored using random cryptographically-generated patterns to detect integrity violations. By using this technology, modifying and rerouting the mesh becomes very costly.

The data travelling through the shield mesh cannot be predicted by the attacker, because it is output by a cryptographic block cipher.

 

Key features

  • Protection against cutting and probing
  • Anti-tamper solution with a mesh placed over the sensitive parts of the circuit (analog/digital/memory) and actively monitored
  • Uses randomly cryptographically-generated patterns to detect integrity violations
  • Mesh can be interleaved with P/G network in topmost layers (no need to sacrifice a layer)
  • Easy to integrate (STA, DRC, Antenna clean, JTAG)
  • Lightweight
  • No calibration after design
  • Transferable to any Design Kit
  • AMBA interface

Benefits

  • No dedicated metal layer
  • Compatible with existing power mesh
  • Fully digital and deployable in any Design Kit
  • Strong technical support

Cyber Escort Unit

The Cyber Escort Unit is designed to fill the security gap between software cybersecurity and hardware by escorting step by step the program execution to achieve high execution performances in a secure way, allowing advantageously real-time detection of zero-day attacks. Unique on the market, this product builds the foundation for hardware-enabled cybersecurity.

 

It comprises technologies for detecting and deceiving cyberattacks. This technology acts on-the-fly. Precisely, CyberEU is a two-fold technology aiming to protect against four threats:

 

  • Return oriented programming (ROP), Jump Oriented Programming (JOP): The attacker reuses chunk of code to assemble a malicious program as a patchwork.
  • Stack Smashing, by exploiting a buffer over run or integer under-or-overflow etc.: the attacker crafts some fake stack frames in order to change the program context.
  • Executable Code Modification, overwrite: the attacker manages to change the genuine program into a malicious program.
  • Control Flow hijacking: the attacker manipulates the program so that it calls an illicit function, or it takes an illicit branch.

 

Key features

  • Hardware protection on processor
  • Compliant with all processor families
  • Escort step by step the program execution
  • Protection against Cyber-attack (ROP, JOP, Buffer overrun, etc.) and Fault Injection attack targeting the code execution
  • Real-time detection of Zero Day attack
  • Stops the attack before it is executed

 

Benefits

  • Easy to integrate
  • No processor modification
  • Agnostic for the program
  • Fully digital
  • AMBA interface
  • Strong technical support

Hash Function

The Hash Algorithm (SHA) family includes MD5, SHA-1, SHA-2, SHA-3, SM3, Whirlpool.

 

In 2012, the algorithm Keccak developed by a Western European team was selected as the winner of the NIST contest and became the new hash function standard known as SHA-3.

 

Whirlpool is a hash function which construction is based on a substantially modified Advanced Encryption Standard architecture. It takes a message of any length less than 2256 bits and returns a 512-bit message digest.

 

The SM3 hash algorithm is a cryptographic hash function designed by the Chinese Commercial Cryptography Administration Office (CCCAO) in order to propose new standard for digital signature generation. The SM3 algorithm is very close to the FIPS SHA-256 algorithm.

 

 

The HMAC hardware module allows performing NIST HMAC algorithms as standardized in the FIPS 198-1. The module is coupled with one of the standard hash algorithm, SHA-1, SHA-256, SHA-384, SHA-512, SHA3-224, SHA3-256, SHA3-384, SHA3-512 or SM3 to produce a tag.

 

 

Key features (all mixed)

  • Tunable performance (area and performance) – From low area to high-performance
  • SCA Protected
  • FIPS, GM/T 0004-2021, GB/T 32905-2016 compliant

 

Benefits

  • Easy to integrate
  • Tunable solution
  • Fully digital
  • AMBA interface
  • Strong technical support

Cipher Function

The Advanced Encryption Standard (AES) is a specification for the encryption of electronic data established by the U.S National Institute of Standards and Technology (NIST) in 2001. It is included in the ISO/IEC 18033-3 standard.

AES is a symmetric-key algorithm, meaning the same key is used for both encrypting and decrypting.

 

The Data Encryption Standard (DES) is defined in FIPS PUB 46-3 as a symmetric-key algorithm. The triple DES (TDES) is block cipher that applies the DES algorithm three times to each data block. The TDES is defined in ANS X9.52-1998, NIST SP 800-67 rev-1 and ISO/IEC 18033-3:2010.

TDES is a symmetric-key algorithm, meaning the same key is used for both encrypting and decrypting.

 

SM4 is a standardized block cipher used in the Chinese National Standards.

 

Key features

 

  • AES supported key sizes: 128, 192 and 256 bits
  • Multiple modes supported: ECB, CBC, CFB, OFB, CTR, CMAC, CCM, GMAC, GCM, XTS
  • Supported operations: DES, 3DES (TDES112, TDES168)
  • Compliant with NIST SP 800-38 / FIPS PUB 46-3, NIST SP800-67 / GM/T 0002-2012 and GBT.32907-2016
  • Tunable performance (area and performance) – From low area to high-performance
  • Secure-IC patented SCA countermeasures
  • Additional cipher functions available: RC4, Kasumi, Chacha20, ARIA, etc.

 

 

Benefits

  • Easy to integrate
  • Tunable solution
  • Fully digital
  • AMBA interface
  • Strong technical support

PKC-RSA/ECC

This PKC IP provides comprehensive ECC and/or RSA encryption / decryption / signature / verification functionalities with hardware acceleration for modular arithmetic operations.

The RSA IP is composed of two parts:

  • The RSA Software library which is run on the host CPU. This CPU can be the main CPU or a dedicated CPU (can be provided by Secure-IC).
  • The RSA Hardware accelerator and its dedicated RAM.

 

A benefit of using elliptic curve cryptography is a smaller key size than RSA-based system to provide the same level of security. For example, a 256-bit elliptic curve public key provides the same level of security than a 3072-bit RSA public key.

The ECC IP provides secure ECC primitives such as signature/verification with ECDSA and SM2, with hardware acceleration for modular arithmetic operations.

The ECC IP is composed of two parts:

  • The ECC Software library which is run on the host CPU. This CPU can be the main CPU or a dedicated CPU (can be provided by Secure-IC).
  • The ECC Hardware accelerator and its dedicated RAM.

 

Key features

  • RSA up to 4096-bit key length
  • ECC up to 521-bit key length
  • Multiples primitives and protocols supported: ECDH, ECDHE, ECDSA, EdDSA, DH, SM2, etc.
  • Tunable solution (area and performance) – From low area to high performance
  • Tunable CPU offload (up to 100%)
  • Secure-IC patented SCA countermeasures

 

Benefits

  • Hardware segregation with a mailbox
  • Easy to integrate
  • Tunable solution
  • Fully digital
  • AMBA interface
  • Strong technical support

Memory Ciphering

Memory protection IP protects the memory content against reverse engineering and tampering.

 

  • Compliant with any kind of memory: DDR, ROM, OTP, Flash, etc.
  • Protecting raw memory content from malevolent access
  • Available with zero latency or high frequency
  • Light implementation
  • Fault injection detection available as an option

 

Key features

  • Encryption/decryption of the memory content
  • Optional integrity of the memory content
  • Optional address scrambling
  • Encryption/decryption based on AES or Lightweight cryptography
  • Low latency
  • Tunable performances (throughput, area, latency)

 

Benefits

  • Easy to integrate
  • Tunable solution
  • Fully digital
  • AMBA interface
  • Strong technical support