Silicon Creations

Our Ring-PLL IP Family is in production from 180nm to 3nm and includes:

– Fractional-N PLLs with a 24-bit delta-sigma modulator allowing the output frequency to be adjusted in steps smaller than 0.01ppm. The rich assortment of input, output and feedback dividers give this PLL an extremely wide operational range enabling software-controlled power-performance tradeoffs and allowing it to be used for many purposes ranging from digital and spread spectrum clocking to ADC clocking.

– Extremely low area (e.g. 0.015mm2) ring PLLs running from core voltage only optimized for clocking digital circuits.

– High-speed, performance optimized integer PLLs with integrated jitter as low as 1ps RMS and suitable for clocking precision data converters and SerDes.

– Fully integrated Jitter Attenuator (jitter cleaner) PLLs optimized for Clock De-spreading, PON, OTU and Synchronous Ethernet applications.

– Multi-phase PLLs providing 12, 16 or even 32 outputs with accurately spaced phase suitable for phase alignment in source-synchronous data interfaces like DDR2, DDR3 and DDR4.

Our Advanced Integer LC-PLLs with digital architecture supporting an LC-Tank are proven in 7nm FinFET and commencing production. These IPs are low power (below 10mW), small (below 0.1mm2) and can provide broadband jitter comfortably below 300fs RMS. Available today on TSMC 6/7FF and 12/16FFC, GF22FDX, and Intel3 process nodes.

Our 28nm Fractional-N synthesizers in production in TSMC, UMC and SMIC with generated LTJ below 500fs RMS broadband and below 150fs RMS integrated above 1MHz.

Our NRZ SerDes architecture is in production in processes ranging from 180nm to 4nm and at rates from 100Mb/s to over 32Gb/s. We offer PMAs targeting several protocols, including JESD204B/C, CPRI1-9, PCIe1/2/3/4/5, OTN, OIF-CEI, 10G-KR, 25G-KR, V-by-One HS, (e)DP, XAUI, SGMII, InfiniBand and Serial RapidIO, a Multiprotocol PMA covering over 30 protocols from 250Mb/s to 32Gb/s, with programmable serialization, de-serialization widths, programmable trim termination, and comprehensive power-down control to optimize power. Our SerDes are also designed for custom requirements such as reduced serializer and deserializer Datapath latency.

LVDS based IO’s

Silicon Creations Bi-directional LVDS is silicon proven and is highly programmable and is an excellent IO for FPGA to ASIC conversions. Features include:

– TIA/EIA644A LVDS, and sub-LVDS compatibility
– Operates at up to 3Gb/s
– Trimmable on-die termination
– Independent LVCMOS input functions

– Minimal, or no additional on-chip supply decoupling required

LVDS based Interfaces

Based on this versatile LVDS circuit and our robust PLLs and CDR architecture we developed multiple uni-directional and bi-directional parallel source-synchronous interfaces for Chip-chip and Video data transmission. These interfaces can comply with custom chip-chip (or chip-FPGA) requirements or standards including HDI, FPDLink, FastLVDS, miniLVDS, TMDS, FPD Link, Camera Link and OpenLDI.  A dynamic phase alignment and robust word alignment architecture enables data rates exceeding 190Mpixels/s (1.33Gb/s in each lane). 

We have a range of free running oscillators for use as watch-dog timers and core clock generators for MCUs and low-power chips with competitive features. These are available off the shelf and in production from 3nm to 65nm, or custom designed for specific targets:

Circuit uses no external components and only baseline CMOS logic process masks and can be optimized for:

– Power < 30uW

– Accuracy better than ±1.5% over -40°C to 125°C and Vdd ±10% and product life after trimming for process

– Period jitter of less than 2%