Silicon Creations


Silicon Creations has a wide portfolio of precision and general purpose timing (PLLs), Free-running oscillators, Chip-chip SerDes and high-speed differential IOs. Our IP is in mass production in hundreds of production chips from 180nm to 16nm and proven in both 10nm and 7nm.


We have a comprehensive and reliable development flow and extensive characterization data for our IP. With a complete commitment to our customer success our support will delight you. The solid partnerships we build with our repeat customers has given us and them an excellent record of first silicon to mass production in their designs.

IP Cores

Ring Based PLL’s

Our Ring-PLL IP Family is in production from 180nm to 16nm and proven in both 10nm and 7nm and includes:

– Fractional-N PLLs with a 24-bit delta-sigma modulator allowing the output frequency to be adjusted in steps smaller than 0.01ppm. The rich assortment of input, output and feedback dividers give this PLL an extremely wide operational range enabling software-controlled power-performance tradeoffs and allowing it to be used for many purposes ranging from digital and spread spectrum clocking to ADC clocking.

– Extremely low area (e.g. 0.015mm2) ring PLLs running from core voltage only optimized for clocking digital circuits.
– High-speed, performance optimized integer PLLs with integrated jitter as low as 1ps RMS and suitable for clocking precision data converters and SerDes, yet using a fraction of the die area needed for an LC-PLL.
– Fully integrated Jitter Attenuator (jitter cleaner) PLLs optimized for Clock De-spreading, PON, OTU and Synchronous Ethernet applications.
– Multi-phase PLLs providing 12, 16 or even 32 outputs with accurately spaced phase suitable for phase alignment in source-synchronous data interfaces like DDR2, DDR3 and DDR4.


LC-based PLLs have historically been difficult to design due to poor modeling of integrated inductance, substrate losses, and package parasitics. In addition, classical LC PLLs have a very narrow frequency tuning range making it possible that the VCO will not be capable of oscillation at the desired frequency. However, Silicon Creations has overcome these problems in two ways:


– First, a high quality coarse tuning element is used which gives a single VCO a wide tuning range to overcome PVT variations and model inaccuracy.

– Additionally, a multiple VCO core design has been developed and can be used to cover up to a 2:1 frequency range.
Silicon Creations has LC PLL designs in technologies from 28nm to 180nm CMOS and with frequencies from 1.4GHz to 8.25GHz. Applications range from optical communications to RF synthesis.

SerDes Interfaces

Our SerDes architecture is in production in processes ranging from 180nm to 28nm and at rates from 100Mb/s to over 12.5Gb/s. We offer targeted PHYs including JESD204, XAUI, CPRI, SGMII, CPRI, OIF-CEI, V-by-One HS, Infiniband and Serial RapidIO, a Multiprotocol PMA covering over 30 protocols from 250Mb/s to 12.7Gb/s and SerDes designed for custom requirements.

LVDS Interfaces

LVDS based IO’s


Silicon Creations Bi-directional LVDS is silicon proven and is highly programmable and is an excellent IO for FPGA to ASIC conversions. Features include:


– TIA/EIA644A LVDS and sub-LVDS compatibility
– Operates at up to 3Gb/s in some processes
– Trimmable on-die termination
– Independent LVCMOS input functions


LVDS based Interfaces

Based on this versatile LVDS circuit and our robust PLLs and CDR architecture we developed multiple uni-directional and bi-directional parallel source-synchronous interfaces for Chip-chip and Video data transmission. These interfaces can comply with custom chip-chip (or chip-FPGA) requirements or standards including HDI, FPDLink, FastLVDS, miniLVDS, TMDS, FPD Link, Camera Link and OpenLDI.  A dynamic phase alignment and robust word alignment architecture enables data rates exceeding 190Mpixels/s (1.33Gb/s in each lane).


Free Running Oscillators


We have a range of free running oscillators for use as watch-dog timers and core clock generators for MCUs and low-power chips with competitive features. These are available off the shelf and in production from 10nm to 65nm, or custom designed for specific targets:


Circuit uses no external components and only baseline CMOS logic process masks and can be optimized for:


– Power < 30uW

– Accuracy better than ±1.5% over -40°C to 125°C and Vdd ±10% and product life after trimming for process

– Period jitter of less than 1%