SkyeChip is a Malaysia-based design company founded by a group of world class IC designers with an average experience of more than 15 years in renowned MNCs and equipped with in-depth and complete technical expertise to develop advanced IP and ASIC products, encompassing architecture, micro-architecture, logic design, circuit design, DFT, physical design, layout, test and product engineering. In addition, the SkyeChip team also has extensive experience in project management, new product introduction, and management of global supply chain for volume production.


SkyeChip also offers the following advanced IPs for licensing:

  • Memory controller & PHY IPs (HBM3, DDR5/4)
  • Interconnect IPs (coherent/non-coherent NOC, 2.5D/3D die-to-die interconnects)
  • Analog IPs (high speed PLL, bandgap)
  • I/Os (MIPI D-PHY, configurable I/Os)
  • RISC-V processor IP cores


SkyeChip portfolio specialization:

  • Solutions from 180nm down to 6/7nm encompassing both digital and analog/custom design
  • Validation and characterization
  • Production IC fabrication with TSMC and GlobalFoundries


Advanced ASIC Development

SkyeChip ASIC team consists of highly accomplished IC designers with successful careers in designing multiple generations of microprocessors, chipsets, ASICs, FPGAs and SoCs from 180nm down to 6/7nm process nodes. We offer:


– Architecture and microarchitecture definition from specification and usage model provided

– Logic and/or circuit design based on the architecture and microarchitecture defined or provided

– Physical design and/or custom layout from the logic and/or circuit design done or provided

– DFT insertion for the ASIC development

– ASIC tapeout for TSMC and GlobalFoundries

New Product Introduction (NPI) Engineering

SkyeChip products are developed to maximize supply chain efficiency and predictability with robust yields. Our team of NPI experts will ensure proper new product introduction that is crucially tied to your product’s successful launch. The NPI team specialize in rapid prototyping and NPI services. Customers can fully rely on us from initial design analysis through productization readiness. This is achieved by ensuring the new products meet the specifications, pass the quality and reliability requirements, characterized to identify the optimum process target, and ready for stable and predictable production. We offer:


NPI Planning – mask tooling, fabrication and silicon out tracking, substrate and piece parts procurement, coordination of vendors, hardware delivery and assembly of prototypes, first silicon and split lots ordering and management


Test Engineering – test & sort pattern and hardware development, first silicon checkout, PVT characterization, ATE vs system correlations


Product Engineering – product qualification, split lots definition, test program development and release, fab process recipe identification, MTTF & FIT estimation through reliability model, test yield improvement, production test management

High Volume Manufacturing (HVM) Enablement

We offer customers high quality manufacturing enablement solutions through collaborations with world class foundries, packaging and assembly & test partners to expedite production startups with good quality and robust yields. SkyeChip’s operations engineering team consists of product, test and quality & reliability engineers to ensure a cost-effective, predictable and high-quality product delivery. SkyeChip’s supply chain analysts perform planning, vendor selection and loading, output monitoring, and inventory management to ensure on-time product delivery and fulfilling end-customer demands.

IP Cores

HBM3 PHY & Controller

Bandwidth and area optimized low power memory interface solution tuned for AI, HPC, data centers and networking conforming to HBM3 JEDEC standards:


– One stop PHY & Controller solution with an average random efficiency of more than 85%

– Supports up to 6400 MT/s

– DFI 5.0 compatible interface to the memory controller

– Flexible PHY with programmable intelligent interface training sequences

– Flexible IEEE1500 interface to support memory vendor customizations

– Supports up to 32Gb density per die

– Supports up to 16H HBM3 DRAM stacks

– Supports major 2.5D/3D packaging technologies including support for interposer designs and interconnect and memory repairs

– Add-on features/engines for MPFE, RAS and Debug available upon request

– Add-on feature for generic 2.5D die-to-die data transport interconnect

Non-Coherent Network-on-Chip (NOC)

Performance (bandwidth and latency) optimized non-coherent NOC solution that significantly reduces silicon wire utilization, resulting in power and area efficient ICs


– Node Protocols: AXI4, AXI5, AXI-Stream, APB, AHB and proprietary protocols

– Architected to reduce routing congestion and to ease high frequency timing closure

– Supports operating frequencies up to 2GHz

– Supports source synchronous and synchronous clocking topologies

– Supports 2.5D and 3D die-to-die NOC bridging

– Integrates seamlessly with SkyeChip’s Coherent NOC for partitioned interconnect systems

Coherent Network-on-Chip (NOC)

Scalable and area efficient interconnect solution optimized for memory coherent systems


– Node Protocols: ACE4, ACE5 and CHI

– Architected to significantly reduce routing congestion for many-core systems

– Integrated with SkyeChip’s Home Agent and swappable with any other proprietary coherency handlers

– Supports operating frequencies up to 2GHz with assists in high frequency timing closures

– Supports source synchronous and synchronous clocking topologies

– Integrates seamlessly with SkyeChip’s Non-Coherent NOC for partitioned interconnect systems

DDR5/4 PHY & Controller

High performance, low power and area efficient memory interface solutions conforming to DDR5 (JESD79-5) and DDR4 (JESD79-4) JEDEC standards


– One stop PHY & Controller solution with an average random efficiency of more than 85%

– Supports up to 4800 MT/s rates with upgradable option to 6400 MT/s

– DFI 5.0 compliant interface to the memory controller

– I/Os include receiver decision feedback equalization (DFE) and transmitter feed forward equalization (FFE)

– Flexible PHY with programmable intelligent interface training sequences

– Supports x4, x8 and x16 SDRAMs

– Supports up to 64Gb addressing for DDR5 and up to 32Gb addressing for DDR4

– Supports 3DS extensions up to 16H for DDR5 and up to 8H for DDR4

– Supports up to 4 ranks for components, UDIMM, RDIMM and LRDIMM

– Add-on features/engines for MPFE, RAS, Ping-Pong and Debug available upon request

Die-to-Die (D2D) Interconnect

Lightweight die-to-die interconnect solution optimized for highest performance with the lowest power and area overhead


– Adaptable to any communication protocols including extending SkyeChip’s Non-Coherent and Coherent NOC interconnects across multiple dies

– Architected to significantly reduce wiring overhead across multiple dies

– Supports transfer rates of up to 6.4GT/s

– Supports major 2.5D and 3D inter-die packaging technologies

Analog & Configurable I/Os

High-Speed PLL

– Reference clock frequency range from 100MHz to 350MHz

– FBDIV range: 2 – 32 (0.5 division)

– POSTDIV range: 1, 2, 4, 8

– VCO frequency can support range from 1.5GHz to 3.2GHz

– Output frequency range: 300MHz – 3.2GHz



– Output Voltage: 0.9V +/- 1%

– Output Current: 50uA +/- 10%

– Buffer Strength: Up to 100uA sink load

– Operating Temperature: -40°C to 125°C

– Power Consumption: Less than 500uW



– Compliant with the MIPI D-PHY spec v2.5

– Fully integrated hard macro with lane control and interface logic

– Up to 1.5 Gbps per lane with upgradable option to 2.5 Gbps per lane

– Supports PHY Protocol Interface (PPI)

– Low-power escape modes and ultra low-power state modes


Configurable I/O

– High-speed configurable I/O capable of signaling speeds of up to 3.2 GT/s supporting the following I/O standards

– LVDS 1.5V

– HCSL 1.2V

– POD 1.1V & 1.2V


– LVSTL 1.1V

– LVCMOS 1.2V/1.5V