SmartSoC Solutions

• RTL Design for Logic IPs
• FC Integration
• SOC Design
• Multi-Core design
• Multip-Power Domain
• Low Power Design
• CDC, LINT qualification
• Synthesis and Timing Constraints

Verification Team at SmortSoC has wide range experience from Verification of IP to SOC. Complete ownership from coding of VIPs to SOC verification.

• IP Verification
• VIP – Development
• Verification Environment Development
• SOC Verification
• Power Intent Verification
• Formal Verification
• Gate Level Simulations
• Mixed Signal Simulations

Architecture Definition to DFT Implementation, Silicon Bring up and Silicon Qualification

• Insertion of all DFT related IPs (JTAG, EDT, OCC)
• Insertion of SCAN, Logic BIST, Memory-BIST
• FUSE implementation and Fuse Controllers integration
• Implementation of BSCAN for all IOs
• Mission Mode Insertion, Compression
• Verification of all DFT insertion
• Test Content / Test Vectors for Production needs
• ATPG
• ATE Vector generation

Complete Ownership from Netlist to GDS of SOC. Delivered various SOC chips and Chipsets ranging from HPC, Automotive application, IOT and Industrial applications.

• APR of Logic Block
• Physical Verification
• STA
• Die-Size Estimation
• IO Ring for Bond Pads and Flip Chips
• Full Chip Integration
• Full Chip Timing Closure and Sign-Off
• GDSII: Mock and Final Tape-out
• Interface facilitation with Fab and OSAT

SmartSoC Analog IP design team has expertise from Architecture to Design and Delivery of complete Analog IP requirement. Analog IP delivered from Industry Application to IOT to Automotive applications.

• Expertise on CMOS/FinFET process node: 5nm, 7nm, 10nm, 14nm, 22nm, 45nm, 65nm, 90nm, 130nm, and 180nm
• ASA (Automotive Serdes Alliance) 16Gbps, PAM-4
• eDP v1.4, MIPI (APHY, DPHY, CPHY)
• ADC, DAC, PLL, Oscillators, GPIO,
• Verilog-A & V-AMS Modelling

• Analog IP Architecture, Design and Delivery
• IO Design and Analog Layout
• Analog IP Technology Porting

Enablement of Silicon-Bring and taking the silicon through qualification

-Transactor Modelling

-Pre-Silicon RTL verification environment porting to Emulation

-Validation

• FPGA Prototype
• Hardware and Software Integration
• SOC Bring Up
• Field Testing

-Testing

• Failure Analysis
• Yield Improvement
• Test Time Optimization

-Coverage Improvement